IDELAYCTRL - 2023.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2023-05-17
Version
2023.1 English

Primitive: IDELAYE3/ODELAYE3 Tap Delay Value Control

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: DELAY
  • Families: UltraScale, UltraScale+

Introduction

At least one of these design elements must be instantiated when using IDELAYE3 or ODELAYE3. The IDELAYCTRL module provides a reference clock input that allows internal circuitry to define precise delay tap values independent of PVT (process, voltage, and temperature) for the IDELAYE3 and ODELAYE3 components.

Port Descriptions

Port Direction Width Function
RDY Output 1 The ready (RDY) signal indicates when IDELAYE3 and ODELAYE3 modules in the specific region are calibrated. The RDY signal is deasserted if REFCLK is held High or Low for one clock more. If RDY is deasserted Low, the IDELAYCTRL module must be reset. If not needed, RDY to be unconnected/ignored.
REFCLK Input 1 Time reference to IDELAYCTRL to calibrate all IDELAYE3 and ODELAYE3 modules in the same region. REFCLK can be supplied directly from a user-supplied source or the MMCME3/PLLE3 and must be routed on a global clock buffer.
RST Input 1 Active-High reset. Asynchronous assertion, synchronous deassertion to REFCLK. To ensure proper IDELAYE3 and ODELAYE3 operation, IDELAYCTRL must be reset after configuration and the REFCLK signal is stable.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog Yes

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- IDELAYCTRL: IDELAYE3/ODELAYE3 Tap Delay Value Control
--             UltraScale
-- Xilinx HDL Language Template, version 2023.1

IDELAYCTRL_inst : IDELAYCTRL
generic map (
   SIM_DEVICE => "ULTRASCALE"  -- Set the device version for simulation functionality (ULTRASCALE)
)
port map (
   RDY => RDY,       -- 1-bit output: Ready output
   REFCLK => REFCLK, -- 1-bit input: Reference clock input
   RST => RST        -- 1-bit input: Active-High reset input. Asynchronous assert, synchronous deassert to
                     -- REFCLK.

);

-- End of IDELAYCTRL_inst instantiation

Verilog Instantiation Template


// IDELAYCTRL: IDELAYE3/ODELAYE3 Tap Delay Value Control
//             UltraScale
// Xilinx HDL Language Template, version 2023.1

IDELAYCTRL #(
   .SIM_DEVICE("ULTRASCALE")  // Set the device version for simulation functionality (ULTRASCALE)
)
IDELAYCTRL_inst (
   .RDY(RDY),       // 1-bit output: Ready output
   .REFCLK(REFCLK), // 1-bit input: Reference clock input
   .RST(RST)        // 1-bit input: Active-High reset input. Asynchronous assert, synchronous deassert to
                    // REFCLK.

);

// End of IDELAYCTRL_inst instantiation

Related Information

  • UltraScale Architecture SelectIO Resources User Guide (UG571)