IOBUFDS_DIFF_OUT - 2023.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2023-05-17
Version
2023.1 English

Primitive: Differential Input/Output Buffer Primitive With Complementary Outputs for the Input Buffer

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: BIDIR_BUFFER
  • Families: UltraScale, UltraScale+

Introduction

The IOBUFDS_DIFF_OUT is a differential input/output buffer primitive with complementary outputs (O and OB). A logic-High on the T pin disables the output buffer. When the output buffer is 3-stated (T = High), the input buffer and any on-die receiver termination (uncalibrated or DCI) are ON. When the output buffer is not 3-stated (T = Low), any on-die receiver termination (uncalibrated or DCI) is disabled. TM and TS must be connected to the same input from the interconnect logic for this primitive to have the expected behavior that is specific to the architecture.

I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DIFF_TERM, and IBUF_LOW_PWR, should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).

Port Descriptions

Port Direction Width Function
I Input 1 Input of OBUF. Connect to the logic driving the output port.
IO Inout 1 Bidirectional diff_p port to be connected directly to top-level inout port.
IOB Inout 1 Bidirectional diff_n port to be connected directly to top-level inout port.
O Output 1 Output path of the buffer.
OB Output 1 Output path of the buffer.
TM Input 1 3-state enable input for the p-side or master side signifying whether the buffer acts as an input or output. This pin must be connected to the same signal as the TS input.
TS Input 1 3-state enable input for the n-side or slave side signifying whether the buffer acts as an input or output. This pin must be connected to the same signal as the TM input.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog No

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- IOBUFDS_DIFF_OUT: Differential Input/Output Buffer Primitive With Complementary Outputs for the Input Buffer
--                   UltraScale
-- Xilinx HDL Language Template, version 2023.1

IOBUFDS_DIFF_OUT_inst : IOBUFDS_DIFF_OUT
port map (
   O => O,     -- 1-bit output: Buffer diff_p output
   OB => OB,   -- 1-bit output: Buffer diff_n output
   I => I,     -- 1-bit input: Buffer input
   IO => IO,   -- 1-bit inout: Diff_p inout (connect directly to top-level port)
   IOB => IOB, -- 1-bit inout: Diff_n inout (connect directly to top-level port)
   TM => TM,   -- 1-bit input: 3-state master enable input
   TS => TS    -- 1-bit input: 3-state slave enable input
);

-- End of IOBUFDS_DIFF_OUT_inst instantiation

Verilog Instantiation Template


// IOBUFDS_DIFF_OUT: Differential Input/Output Buffer Primitive With Complementary Outputs for the Input Buffer
//                   UltraScale
// Xilinx HDL Language Template, version 2023.1

IOBUFDS_DIFF_OUT IOBUFDS_DIFF_OUT_inst (
   .O(O),     // 1-bit output: Buffer diff_p output
   .OB(OB),   // 1-bit output: Buffer diff_n output
   .I(I),     // 1-bit input: Buffer input
   .IO(IO),   // 1-bit inout: Diff_p inout (connect directly to top-level port)
   .IOB(IOB), // 1-bit inout: Diff_n inout (connect directly to top-level port)
   .TM(TM),   // 1-bit input: 3-state master enable input
   .TS(TS)    // 1-bit input: 3-state slave enable input
);

// End of IOBUFDS_DIFF_OUT_inst instantiation

Related Information

  • UltraScale Architecture SelectIO Resources User Guide (UG571)
  • Vivado Design Suite Properties Reference Guide (UG912)