IOBUFDS_DIFF_OUT_DCIEN - 2023.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2023-05-17
Version
2023.1 English

Primitive: Differential Bidirectional Buffer with Complementary Outputs, Input Path Disable, and On-die Input Termination Disable

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: BIDIR_BUFFER
  • Families: UltraScale, UltraScale+

Introduction

The IOBUFDS_DIFF_OUT_DCIEN primitive is available in the HP I/O banks. It has complementary differential outputs, an IBUFDISABLE port, and a DCITERMDISABLE port that can be used to manually disable the optional DCI on-die receiver termination features (uncalibrated or DCI). See UltraScale Architecture SelectIO Resources User Guide (UG571), "DCI Only available in the HP I/O Banks" and "Uncalibrated Input Termination in I/O Banks" sections for more details. The USE_IBUFDISABLE attribute must be set to TRUE and SIM_DEVICE to the appropriate value for this primitive to have the expected behavior that is specific to the architecture. TM and TS must be connected to the same input from the interconnect logic for this primitive to have the expected behavior that is specific to the architecture.

If the I/O is using any on-die receiver termination features (uncalibrated or DCI), this primitive disables the termination legs whenever the DCITERMDISABLE signal is asserted High and the output buffer is 3-stated. When the output buffer is 3-stated (T = High), any on-die receiver termination (uncalibrated or DCI) is controlled by DCITERMDISABLE. When the output buffer is not 3-stated (T = Low), the input buffer and on-die receiver termination (uncalibrated or DCI) are disabled and the O output (to the internal logic) is forced to a logic-Low.

I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DIFF_TERM, and IBUF_LOW_PWR, should be supplied to the top-level port via an appropriate property. For details on applying such properties to the associated port, see the Vivado Design Suite Properties Reference Guide (UG912).

Port Descriptions

Port Direction Width Function
DCITERMDISABLE Input 1 Control to enable/disable DCI termination. This is generally used to reduce power in long periods of an idle state.
I Input 1 Input of OBUF. Connect to the logic driving the output port.
IBUFDISABLE Input 1 The IBUFDISABLE feature is not supported with this primitive in the UltraScale architecture. This port must be tied to logic '0'.
IO Inout 1 Bidirectional diff_p port to be connected directly to top-level inout port.
IOB Inout 1 Bidirectional diff_n port to be connected directly to top-level inout port.
O Output 1 Output path of the buffer.
OB Output 1 Output path of the buffer.
TM Input 1 3-state enable input for the p-side or master side signifying whether the buffer acts as an input or output. This pin must be connected to the same signal as the TS input.
TS Input 1 3-state enable input for the n-side or slave side signifying whether the buffer acts as an input or output. This pin must be connected to the same signal as the TM input.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
SIM_DEVICE STRING "7SERIES", "ULTRASCALE" "7SERIES" Set the device version for simulation functionality.
USE_IBUFDISABLE STRING "TRUE", "FALSE", "T_CONTROL" "TRUE" This attribute must be unspecified or set to "TRUE" if specified.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- IOBUFDS_DIFF_OUT_DCIEN: Differential Bidirectional Buffer with Complementary Outputs, Input Path Disable, and On-die Input Termination Disable
--                         UltraScale
-- Xilinx HDL Language Template, version 2023.1

IOBUFDS_DIFF_OUT_DCIEN_inst : IOBUFDS_DIFF_OUT_DCIEN
generic map (
   SIM_DEVICE => "ULTRASCALE"  -- Set the device version for simulation functionality (ULTRASCALE)
)
port map (
   O => O,                           -- 1-bit output: Buffer diff_p output
   OB => OB,                         -- 1-bit output: Buffer diff_n output
   DCITERMDISABLE => DCITERMDISABLE, -- 1-bit input: DCI Termination Disable
   I => I,                           -- 1-bit input: Buffer input
   IBUFDISABLE => IBUFDISABLE,       -- 1-bit input: Must be tied to a logic '0'
   IO => IO,                         -- 1-bit inout: Diff_p inout (connect directly to top-level port)
   IOB => IOB,                       -- 1-bit inout: Diff_n inout (connect directly to top-level port)
   TM => TM,                         -- 1-bit input: 3-state master enable input
   TS => TS                          -- 1-bit input: 3-state slave enable input
);

-- End of IOBUFDS_DIFF_OUT_DCIEN_inst instantiation

Verilog Instantiation Template


// IOBUFDS_DIFF_OUT_DCIEN: Differential Bidirectional Buffer with Complementary Outputs, Input Path Disable, and On-die Input Termination Disable
//                         UltraScale
// Xilinx HDL Language Template, version 2023.1

IOBUFDS_DIFF_OUT_DCIEN #(
   .SIM_DEVICE("ULTRASCALE")  // Set the device version for simulation functionality (ULTRASCALE)
)
IOBUFDS_DIFF_OUT_DCIEN_inst (
   .O(O),                           // 1-bit output: Buffer diff_p output
   .OB(OB),                         // 1-bit output: Buffer diff_n output
   .DCITERMDISABLE(DCITERMDISABLE), // 1-bit input: DCI Termination Disable
   .I(I),                           // 1-bit input: Buffer input
   .IBUFDISABLE(IBUFDISABLE),       // 1-bit input: Must be tied to a logic '0'
   .IO(IO),                         // 1-bit inout: Diff_p inout (connect directly to top-level port)
   .IOB(IOB),                       // 1-bit inout: Diff_n inout (connect directly to top-level port)
   .TM(TM),                         // 1-bit input: 3-state master enable input
   .TS(TS)                          // 1-bit input: 3-state slave enable input
);

// End of IOBUFDS_DIFF_OUT_DCIEN_inst instantiation

Related Information

  • UltraScale Architecture SelectIO Resources User Guide (UG571)
  • Vivado Design Suite Properties Reference Guide (UG912)