LUT3 - 2023.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2023-05-17
Version
2023.1 English

Primitive: 3-Bit Look-Up Table

  • PRIMITIVE_GROUP: CLB
  • PRIMITIVE_SUBGROUP: LUT
  • Families: UltraScale, UltraScale+

Introduction

This design element is a 3-bit look-up table (LUT). This element allows the creation of any logical function with three inputs.

The INIT parameter for the LUT primitive is what gives the LUT its logical value. By default, this value is zero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in most cases a new INIT value must be determined in order to specify the logic function for the LUT primitive. There are at least two methods by which the LUT value can be determined:
  • The Logic Table Method: A common method to determine the desired INIT value for a LUT is using a logic table. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of the output and then create the INIT string from those output values.
  • The Equation Method: Another method to determine the LUT value is to define parameters or generics for each input to the LUT that correspond to their listed truth value and use those to build the logic equation you are after. This method is easier to understand once you have grasped the concept and is more self-documenting than the above method. However, this method does require the code to first specify the appropriate parameters or generics.

A LUT3 can be grouped with a LUT1, LUT2, LUT3, LUT4, or LUT5 and placed into a single LUT6 resource, as long as the combined input signals do not exceed five unique inputs. The Vivado Design Suite will automatically combine LUTs when necessary or advantageous. However, this can be manually controlled by specifying a LUTNM or HLUTNM on the associated LUT components to specify specific grouping within a single LUT resource.

Logic Table

Inputs Outputs
I2 I1 I0 O
0 0 0 INIT[0]
0 0 1 INIT[1]
0 1 0 INIT[2]
0 1 1 INIT[3]
1 0 0 INIT[4]
1 0 1 INIT[5]
1 1 0 INIT[6]
1 1 1 INIT[7]
INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute

Design Entry Method

Instantiation Yes
Inference Recommended
IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
INIT HEX 8'h00 to 8'hff 8'h00 Specifies the logical expression of this element.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- LUT3: 3-Bit Look-Up Table
--       UltraScale
-- Xilinx HDL Language Template, version 2023.1

LUT3_inst : LUT3
generic map (
   INIT => X"00"  -- Logic function
)
port map (
   O => O,   -- 1-bit output: LUT
   I0 => I0, -- 1-bit input: LUT
   I1 => I1, -- 1-bit input: LUT
   I2 => I2  -- 1-bit input: LUT
);

-- End of LUT3_inst instantiation

Verilog Instantiation Template


// LUT3: 3-Bit Look-Up Table
//       UltraScale
// Xilinx HDL Language Template, version 2023.1

LUT3 #(
   .INIT(8'h00)  // Logic function
)
LUT3_inst (
   .O(O),   // 1-bit output: LUT
   .I0(I0), // 1-bit input: LUT
   .I1(I1), // 1-bit input: LUT
   .I2(I2)  // 1-bit input: LUT
);

// End of LUT3_inst instantiation

Related Information

  • UltraScale Architecture Configurable Logic Block User Guide (UG574)