PLLE3_ADV - 2023.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2023-05-17
Version
2023.1 English

Primitive: Advanced Phase-Locked Loop (PLL)

  • PRIMITIVE_GROUP: CLOCK
  • PRIMITIVE_SUBGROUP: PLL
  • Families: UltraScale, UltraScale+

Introduction

The PLLE3 is used for high-speed I/O clocking using Bitslice components as well as general clocking requirements. In general, the PLLE3 has less jitter and reduced power characteristics compared to the MMCME3 which makes it preferable for clocking behaviors that do not require features only available to the MMCME3.

Port Descriptions

Port Direction Width Function
CLKIN Input 1 Clock input.
LOCKED Output 1 An output from the PLL that indicates when the PLL has achieved phase alignment within a predefined window and frequency matching within a predefined PPM range. The PLL automatically locks after power on, no extra reset is required. LOCKED will be deasserted if the input clock stops or the phase alignment is violated (for example, input clock phase shift). The PLL must be reset after LOCKED is deasserted.
Clock Outputs: User configurable clock outputs that can be divided versions of the VCO phase outputs (user controllable) from 1 (bypassed) to 256. The output clocks are phase aligned to each other (unless phase shifted) and aligned to the input clock with a proper feedback configuration.
CLKOUTPHY Output 1 General clock output connected to I/O Bitslice components.
CLKOUT0 Output 1 General clock output CLKOUT0. Generally connected to a global buffer.
CLKOUT0B Output 1 Inverted CLKOUT0. Generally connected to a global buffer.
CLKOUT1 Output 1 General clock output CLKOUT1. Generally connected to a global buffer.
CLKOUT1B Output 1 Inverted CLKOUT1. Generally connected to a global buffer.
Control Ports: PLL control ports.
CLKOUTPHYEN Input 1 Enable signal for CLKOUTPHY.
PWRDWN Input 1 Powers down instantiated but unused PLLs.
RST Input 1 The RST signal is an asynchronous reset for the PLL. The PLL will synchronously re-enable itself when this signal is released and go through a new phase alignment and lock cycle. A reset is required when the input clock conditions change (for example, frequency).
DRP Ports: Ports used when using the dynamic reconfigurable ports for reading and writing the configuration of the PLL.
DADDR<6:0> Input 7 The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration address for the dynamic reconfiguration. When not used, all bits must be assigned zeros.
DCLK Input 1 The DCLK signal is the reference clock for the dynamic reconfiguration port.
DEN Input 1 The dynamic reconfiguration enable (DEN) provides the enable control signal to access the dynamic reconfiguration feature. When the dynamic reconfiguration feature is not used, DEN must be tied Low.
DI<15:0> Input 16 The dynamic reconfiguration output bus provides PLL data output when using dynamic reconfiguration.
DO<15:0> Output 16 The dynamic reconfiguration output bus provides PLL data output when using dynamic reconfiguration.
DRDY Output 1 The dynamic reconfiguration ready output (DRDY) provides the response to the DEN signal for the PLLs dynamic reconfiguration feature.
DWE Input 1 The dynamic reconfiguration write enable (DWE) input pin provides the write enable control signal to write the DI data into the DADDR address. When not used, it must be tied Low.
Feedback Clocks: Required ports to form the feedback path for the PLL phase alignment capabilities.
CLKFBIN Input 1 Feedback clock pin to the PLL.
CLKFBOUT Output 1 Dedicated PLL Feedback clock output.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog Recommended

Available Attributes

Attribute Type Allowed Values Default Description
CLKFBOUT_MULT DECIMAL 1 to 19 5 Specifies the amount to multiply all CLKOUT clock outputs if a different frequency is desired. This number, in combination with the associated CLKOUT#_DIVIDE value and DIVCLK_DIVIDE value, will determine the output frequency.
CLKFBOUT_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the clock feedback output. Shifting the feedback clock results in a negative phase shift of all output clocks to the PLL.
CLKIN_PERIOD FLOAT(nS) 0.000 to 14.286 0.000 Specifies the input period in ns to the PLL CLKIN input. Resolution is down to the ps (3 decimal places). For example, a value of 33.333 would indicate a 30 MHz input clock. This information is mandatory and must be supplied.
CLKOUTPHY_MODE STRING "VCO_2X", "VCO", "VCO_HALF" "VCO_2X" Specifies the frequency of the CLKOUTPHY clock output.
COMPENSATION STRING "AUTO", "BUF_IN", "INTERNAL" "AUTO" Clock input compensation. In general, should be set to AUTO. Defines how the PLL feedback compensation is configured.
  • "AUTO": Tools automatically determine proper compensation settings based on how the PLL feedback path is connected.
  • "INTERNAL": Indicates the PLL is using its own internal feedback path so no delay is being compensated.
  • "BUF_IN": Indicates that the clock network delay within the same XIPHY bank is compensated. The feedback must be limited to within the same XIPHY and cannot be routed to adjacent banks or outside the device.
DIVCLK_DIVIDE DECIMAL 1 to 15 1 Specifies the division ratio for all output clocks with respect to the input clock. Effectively divides the CLKIN going into the PFD.
REF_JITTER 3 significant digit FLOAT 0.000 to 0.999 0.010 Allows specification of the expected jitter on CLKIN to better optimize PLL performance. A bandwidth setting of OPTIMIZED will attempt to choose the best parameter for input clocking when unknown. If known, then the value provided should be specified in terms of the UI percentage (the maximum peak to peak value) of the expected jitter on the input clock.
STARTUP_WAIT STRING "FALSE", "TRUE" "FALSE" Delays configuration DONE signal from asserting until PLL is locked.
CLKOUT0 Attributes: Sets the Divide, Phase and Duty Cycle for the CLKOUT0 output.
CLKOUT0_DIVIDE DECIMAL 1 to 128 1 Specifies the amount to divide the CLKOUT0 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency.
CLKOUT0_DUTY_CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the Duty Cycle of CLKOUT0 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle).
CLKOUT0_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the CLKOUT0 output.
CLKOUT1 Attributes: Sets the Divide, Phase and Duty Cycle for the CLKOUT1 output.
CLKOUT1_DIVIDE DECIMAL 1 to 128 1 Specifies the amount to divide the CLKOUT1 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency.
CLKOUT1_DUTY_CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the Duty Cycle of CLKOUT1 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle).
CLKOUT1_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the CLKOUT1 output.
Programmable Inversion Attributes: Specifies whether or not to use the optional inversions on specific pins of this component to change the active polarity of the pin function. When set to 1 on a clock input pin (CLKIN or CLKFBIN), the phase is effectively shifted 180 degrees. When set to 1 on other pins, it changes the function to behave active-Low rather than active-High. If an external inverter is specified on one of these associated pins, the Vivado Design Suite will automatically set this attribute during the opt_design stage so that additional logic is not necessary for changing the input polarity.
IS_CLKFBIN_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKFBIN pin of this component.
IS_CLKIN_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKIN pin of this component.
IS_PWRDWN_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the PWRDWN pin of this component.
IS_RST_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the RST pin of this component.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- PLLE3_ADV: Advanced Phase-Locked Loop (PLL)
--            UltraScale
-- Xilinx HDL Language Template, version 2023.1

PLLE3_ADV_inst : PLLE3_ADV
generic map (
   CLKFBOUT_MULT => 5,         -- Multiply value for all CLKOUT, (1-19)
   CLKFBOUT_PHASE => 0.0,      -- Phase offset in degrees of CLKFB, (-360.000-360.000)
   CLKIN_PERIOD => 0.0,        -- Input clock period in ns to ps resolution (i.e., 33.333 is 30 MHz).
   -- CLKOUT0 Attributes: Divide, Phase and Duty Cycle for the CLKOUT0 output
   CLKOUT0_DIVIDE => 1,        -- Divide amount for CLKOUT0 (1-128)
   CLKOUT0_DUTY_CYCLE => 0.5,  -- Duty cycle for CLKOUT0 (0.001-0.999)
   CLKOUT0_PHASE => 0.0,       -- Phase offset for CLKOUT0 (-360.000-360.000)
   -- CLKOUT1 Attributes: Divide, Phase and Duty Cycle for the CLKOUT1 output
   CLKOUT1_DIVIDE => 1,        -- Divide amount for CLKOUT1 (1-128)
   CLKOUT1_DUTY_CYCLE => 0.5,  -- Duty cycle for CLKOUT1 (0.001-0.999)
   CLKOUT1_PHASE => 0.0,       -- Phase offset for CLKOUT1 (-360.000-360.000)
   CLKOUTPHY_MODE => "VCO_2X", -- Frequency of the CLKOUTPHY (VCO, VCO_2X, VCO_HALF)
   COMPENSATION => "AUTO",     -- AUTO, BUF_IN, INTERNAL
   DIVCLK_DIVIDE => 1,         -- Master division value, (1-15)
   -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
   IS_CLKFBIN_INVERTED => '0', -- Optional inversion for CLKFBIN
   IS_CLKIN_INVERTED => '0',   -- Optional inversion for CLKIN
   IS_PWRDWN_INVERTED => '0',  -- Optional inversion for PWRDWN
   IS_RST_INVERTED => '0',     -- Optional inversion for RST
   REF_JITTER => 0.0,          -- Reference input jitter in UI (0.000-0.999)
   STARTUP_WAIT => "FALSE"     -- Delays DONE until PLL is locked (FALSE, TRUE)
)
port map (
   -- Clock Outputs outputs: User configurable clock outputs
   CLKOUT0 => CLKOUT0,         -- 1-bit output: General Clock output
   CLKOUT0B => CLKOUT0B,       -- 1-bit output: Inverted CLKOUT0
   CLKOUT1 => CLKOUT1,         -- 1-bit output: General Clock output
   CLKOUT1B => CLKOUT1B,       -- 1-bit output: Inverted CLKOUT1
   CLKOUTPHY => CLKOUTPHY,     -- 1-bit output: Bitslice clock
   -- DRP Ports outputs: Dynamic reconfiguration ports
   DO => DO,                   -- 16-bit output: DRP data
   DRDY => DRDY,               -- 1-bit output: DRP ready
   -- Feedback Clocks outputs: Clock feedback ports
   CLKFBOUT => CLKFBOUT,       -- 1-bit output: Feedback clock
   LOCKED => LOCKED,           -- 1-bit output: LOCK
   CLKIN => CLKIN,             -- 1-bit input: Input clock
   -- Control Ports inputs: PLL control ports
   CLKOUTPHYEN => CLKOUTPHYEN, -- 1-bit input: CLKOUTPHY enable
   PWRDWN => PWRDWN,           -- 1-bit input: Power-down
   RST => RST,                 -- 1-bit input: Reset
   -- DRP Ports inputs: Dynamic reconfiguration ports
   DADDR => DADDR,             -- 7-bit input: DRP address
   DCLK => DCLK,               -- 1-bit input: DRP clock
   DEN => DEN,                 -- 1-bit input: DRP enable
   DI => DI,                   -- 16-bit input: DRP data
   DWE => DWE,                 -- 1-bit input: DRP write enable
   -- Feedback Clocks inputs: Clock feedback ports
   CLKFBIN => CLKFBIN          -- 1-bit input: Feedback clock
);

-- End of PLLE3_ADV_inst instantiation

Verilog Instantiation Template


// PLLE3_ADV: Advanced Phase-Locked Loop (PLL)
//            UltraScale
// Xilinx HDL Language Template, version 2023.1

PLLE3_ADV #(
   .CLKFBOUT_MULT(5),          // Multiply value for all CLKOUT, (1-19)
   .CLKFBOUT_PHASE(0.0),       // Phase offset in degrees of CLKFB, (-360.000-360.000)
   .CLKIN_PERIOD(0.0),         // Input clock period in ns to ps resolution (i.e., 33.333 is 30 MHz).
   // CLKOUT0 Attributes: Divide, Phase and Duty Cycle for the CLKOUT0 output
   .CLKOUT0_DIVIDE(1),         // Divide amount for CLKOUT0 (1-128)
   .CLKOUT0_DUTY_CYCLE(0.5),   // Duty cycle for CLKOUT0 (0.001-0.999)
   .CLKOUT0_PHASE(0.0),        // Phase offset for CLKOUT0 (-360.000-360.000)
   // CLKOUT1 Attributes: Divide, Phase and Duty Cycle for the CLKOUT1 output
   .CLKOUT1_DIVIDE(1),         // Divide amount for CLKOUT1 (1-128)
   .CLKOUT1_DUTY_CYCLE(0.5),   // Duty cycle for CLKOUT1 (0.001-0.999)
   .CLKOUT1_PHASE(0.0),        // Phase offset for CLKOUT1 (-360.000-360.000)
   .CLKOUTPHY_MODE("VCO_2X"),  // Frequency of the CLKOUTPHY (VCO, VCO_2X, VCO_HALF)
   .COMPENSATION("AUTO"),      // AUTO, BUF_IN, INTERNAL
   .DIVCLK_DIVIDE(1),          // Master division value, (1-15)
   // Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
   .IS_CLKFBIN_INVERTED(1'b0), // Optional inversion for CLKFBIN
   .IS_CLKIN_INVERTED(1'b0),   // Optional inversion for CLKIN
   .IS_PWRDWN_INVERTED(1'b0),  // Optional inversion for PWRDWN
   .IS_RST_INVERTED(1'b0),     // Optional inversion for RST
   .REF_JITTER(0.0),           // Reference input jitter in UI (0.000-0.999)
   .STARTUP_WAIT("FALSE")      // Delays DONE until PLL is locked (FALSE, TRUE)
)
PLLE3_ADV_inst (
   // Clock Outputs outputs: User configurable clock outputs
   .CLKOUT0(CLKOUT0),         // 1-bit output: General Clock output
   .CLKOUT0B(CLKOUT0B),       // 1-bit output: Inverted CLKOUT0
   .CLKOUT1(CLKOUT1),         // 1-bit output: General Clock output
   .CLKOUT1B(CLKOUT1B),       // 1-bit output: Inverted CLKOUT1
   .CLKOUTPHY(CLKOUTPHY),     // 1-bit output: Bitslice clock
   // DRP Ports outputs: Dynamic reconfiguration ports
   .DO(DO),                   // 16-bit output: DRP data
   .DRDY(DRDY),               // 1-bit output: DRP ready
   // Feedback Clocks outputs: Clock feedback ports
   .CLKFBOUT(CLKFBOUT),       // 1-bit output: Feedback clock
   .LOCKED(LOCKED),           // 1-bit output: LOCK
   .CLKIN(CLKIN),             // 1-bit input: Input clock
   // Control Ports inputs: PLL control ports
   .CLKOUTPHYEN(CLKOUTPHYEN), // 1-bit input: CLKOUTPHY enable
   .PWRDWN(PWRDWN),           // 1-bit input: Power-down
   .RST(RST),                 // 1-bit input: Reset
   // DRP Ports inputs: Dynamic reconfiguration ports
   .DADDR(DADDR),             // 7-bit input: DRP address
   .DCLK(DCLK),               // 1-bit input: DRP clock
   .DEN(DEN),                 // 1-bit input: DRP enable
   .DI(DI),                   // 16-bit input: DRP data
   .DWE(DWE),                 // 1-bit input: DRP write enable
   // Feedback Clocks inputs: Clock feedback ports
   .CLKFBIN(CLKFBIN)          // 1-bit input: Feedback clock
);

// End of PLLE3_ADV_inst instantiation

Related Information

  • UltraScale Architecture Clocking Resources User Guide (UG572)