RAM32M16 - 2023.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2023-05-17
Version
2023.1 English

Primitive: 32-Deep by 16-bit Wide Multi Port Random Access Memory (Select RAM)

  • PRIMITIVE_GROUP: CLB
  • PRIMITIVE_SUBGROUP: LUTRAM
  • Families: UltraScale, UltraScale+

Introduction

This design element is a 32-bit deep by 16-bit wide, multi-port, random access memory with synchronous write and asynchronous independent, 2-bit, wide-read capability. This RAM is implemented using the LUT resources of the device known as SelectRAM™+, and does not consume any of the Block RAM resources of the device. This component is implemented in a single CLB and consists of one 16-bit write, 2-bit read port and seven separate 2-bit read ports from the same memory, which allows for dual byte-wide write and independent 2-bit read access RAM.
  • If the DIA through DIH inputs are all tied to the same data inputs, the RAM can become a 1 read/write port, 7 independent read port, 32x2 eight port memory.

  • If DIH is grounded, DOH is not used.

  • If ADDRA through ADDRG are tied to the same address, the RAM becomes a 32x14 simple dual port RAM.

  • If ADDRA through ADDRH are tied together, the RAM becomes a 32x16 single port RAM.

There are several other possible configurations for this RAM.

Port Descriptions

Port Direction Width Function
DOA Output 2 Read port data outputs addressed by ADDRA
DOB Output 2 Read port data outputs addressed by ADDRB
DOC Output 2 Read port data outputs addressed by ADDRC
DOD Output 2 Read port data outputs addressed by ADDRD
DOE Output 2 Read port data outputs addressed by ADDRE
DOF Output 2 Read port data outputs addressed by ADDRF
DOG Output 2 Read port data outputs addressed by ADDRG
DOH Output 2 Read/Write port data outputs addressed by ADDRH
DIA Input 2 Data write input addressed by ADDRH (read output is addressed by ADDRA)
DIB Input 2 Data write input addressed by ADDRH (read output is addressed by ADDRB)
DIC Input 2 Data write input addressed by ADDRH (read output is addressed by ADDRC)
DID Input 2 Data write input addressed by ADDRH (read output is addressed by ADDRD)
DIE Input 2 Data write input addressed by ADDRH (read output is addressed by ADDRE)
DIF Input 2 Data write input addressed by ADDRH (read output is addressed by ADDRF)
DIG Input 2 Data write input addressed by ADDRH (read output is addressed by ADDRG)
DIH Input 2 RAM 2-bit data write input addressed by ADDRH (read output is addressed by ADDRH)
ADDRA Input 5 Read port A address input
ADDRB Input 5 Read port B address input
ADDRC Input 5 Read port C address input
ADDRD Input 5 Read port D address input
ADDRE Input 5 Read port E address input
ADDRF Input 5 Read port F address input
ADDRG Input 5 Read port G address input
ADDRH Input 5 Read/write port H address input
WE Input 1 Write Enable
WCLK Input 1 Write clock (reads are asynchronous)

Design Entry Method

Instantiation Yes
Inference Recommended
IP Catalog No

This element can be inferred by some synthesis tools by describing a RAM with a synchronous write and asynchronous read capability. Consult your synthesis tool documentation for details on RAM inference capabilities and coding examples. You should instantiate this component if you have a need to implicitly specify the RAM function, or if you need to manually place or relationally place the component.

If synchronous read capability is desired, the outputs can be connected to an FDRE/FDSE (FDCE/FDPE if asynchronous reset is needed) in order to improve the output timing of the function. However, this is not necessary for the proper operation of the RAM. If you want to have the data clocked on the negative edge of a clock, an inverter can be described on the clock input to this component. This inverter will be absorbed into the block during implementation and set as the IS_WCLK_INVERTED attribute giving the ability to write to the RAM on falling clock edges.

If instantiated, the following connections should be made to this component:
  • Connect the WCLK input to the desired clock source

  • Connect the DIA–DIH inputs to the data source to be stored

  • Connect the DOA–DOH outputs to an FD* D input or other appropriate data destination, or leave unconnected if not used

  • Connect the WE clock enable pin to the proper write enable source in the design

  • Connect the ADDRH bus to the source for the read/write addressing

  • Connect the ADDRA–ADDRG buses to the appropriate read address connections

The optional INIT_A–INIT_H attributes let you specify the initial memory contents of each port using a 64-bit hexadecimal value. The INIT value correlates to the RAM addressing by the following equation: ADDRy[z] = INIT_y[2*z+1:2*z]. For instance, if the RAM ADDRC port is addressed to 00001, then the INIT_C[3:2] values would be the initial values shown on the DOC port before the first write occurs at that address. If left unspecified, the initial contents will be all zeros.

Available Attributes

Attribute Type Allowed Values Default Description
INIT_A HEX Any 128-bit value All zeros Specifies the initial contents of the RAM on port A.
INIT_B HEX Any 128-bit value All zeros Specifies the initial contents of the RAM on port B.
INIT_C HEX Any 128-bit value All zeros Specifies the initial contents of the RAM on port C.
INIT_D HEX Any 128-bit value All zeros Specifies the initial contents of the RAM on port D.
INIT_E HEX Any 128-bit value All zeros Specifies the initial contents of the RAM on port E.
INIT_F HEX Any 128-bit value All zeros Specifies the initial contents of the RAM on port F.
INIT_G HEX Any 128-bit value All zeros Specifies the initial contents of the RAM on port G.
INIT_H HEX Any 128-bit value All zeros Specifies the initial contents of the RAM on port H.
IS_WCLK_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the WCLK pin.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- RAM32M16: 32-deep by 16-wide Multi Port LUT RAM
--           UltraScale
-- Xilinx HDL Language Template, version 2023.1
 RAM32M16_inst : RAM32M16
generic map (
   INIT_A => X"0000000000000000",   -- Initial contents of A port
   INIT_B => X"0000000000000000",   -- Initial contents of B port
   INIT_C => X"0000000000000000",   -- Initial contents of C port
   INIT_D => X"0000000000000000",   -- Initial contents of D port
   INIT_E => X"0000000000000000",   -- Initial contents of E port
   INIT_F => X"0000000000000000",   -- Initial contents of F port
   INIT_G => X"0000000000000000",   -- Initial contents of G port
   INIT_H => X"0000000000000000",   -- Initial contents of H port
   IS_WCLK_INVERTED => '0') -- Specifies active high/low WCLK
port map (
   DOA => DOA, -- Read port A 2-bit output
   DOB => DOB, -- Read port B 2-bit output
   DOC => DOC, -- Read port C 2-bit output
   DOD => DOD, -- Read port D 2-bit output
   DOE => DOE, -- Read port E 2-bit output
   DOF => DOF, -- Read port F 2-bit output
   DOG => DOG, -- Read port G 2-bit output
   DOH => DOH, -- Read/write port H 2-bit output
   ADDRA => ADDRA,   -- Read port A 5-bit address input
   ADDRB => ADDRB,   -- Read port B 5-bit address input
   ADDRC => ADDRC,   -- Read port C 5-bit address input
   ADDRD => ADDRD,   -- Read port D 5-bit address input
   ADDRE => ADDRE,   -- Read port E 5-bit address input
   ADDRF => ADDRF,   -- Read port F 5-bit address input
   ADDRG => ADDRG,   -- Read port G 5-bit address input
   ADDRH => ADDRH,   -- Read/write port H 5-bit address input
   DIA => DIA,       -- RAM 2-bit data write input addressed by ADDRH,
                     -- read addressed by ADDRA
   DIB => DIB,       -- RAM 2-bit data write input addressed by ADDRH,
                     -- read addressed by ADDRB
   DIC => DIC,       -- RAM 2-bit data write input addressed by ADDRH,
                     -- read addressed by ADDRC
   DID => DID,       -- RAM 2-bit data write input addressed by ADDRH,
                     -- read addressed by ADDRD
   DIE => DIE,       -- RAM 2-bit data write input addressed by ADDRH,
                     -- read addressed by ADDRE
   DIF => DIF,       -- RAM 2-bit data write input addressed by ADDRH,
                     -- read addressed by ADDRF
   DIG => DIG,       -- RAM 2-bit data write input addressed by ADDRH,
                     -- read addressed by ADDRG
   DIH => DIH,       -- RAM 2-bit data write input addressed by ADDRH,
                     -- read addressed by ADDRH
   WCLK => WCLK,  -- Write clock input
   WE => WE       -- Write enable input
);
-- End of RAM32M16_inst instantiation

Verilog Instantiation Template


// RAM32M16: 32-deep by 16-wide Multi Port LUT RAM (Mapped to eight LUT6s)
//           UltraScale
// Xilinx HDL Language Template, version 2023.1

RAM32M16 #(
   .INIT_A(64'h0000000000000000), // Initial contents of A Port
   .INIT_B(64'h0000000000000000), // Initial contents of B Port
   .INIT_C(64'h0000000000000000), // Initial contents of C Port
   .INIT_D(64'h0000000000000000), // Initial contents of D Port
   .INIT_E(64'h0000000000000000), // Initial contents of E Port
   .INIT_F(64'h0000000000000000), // Initial contents of F Port
   .INIT_G(64'h0000000000000000), // Initial contents of G Port
   .INIT_H(64'h0000000000000000), // Initial contents of H Port
   .IS_WCLK_INVERTED(1'b0)        // Specifies active high/low WCLK
) RAM32M16_inst (
   .DOA(DOA),     // Read port A 2-bit output
   .DOB(DOB),     // Read port B 2-bit output
   .DOC(DOC),     // Read port C 2-bit output
   .DOD(DOD),     // Read port D 2-bit output
   .DOE(DOE),     // Read port E 2-bit output
   .DOF(DOF),     // Read port F 2-bit output
   .DOG(DOG),     // Read port G 2-bit output
   .DOH(DOH),     // Read/write port H 2-bit output
   .ADDRA(ADDRA), // Read port A 5-bit address input
   .ADDRB(ADDRB), // Read port B 5-bit address input
   .ADDRC(ADDRC), // Read port C 5-bit address input
   .ADDRD(ADDRD), // Read port D 5-bit address input
   .ADDRE(ADDRE), // Read port E 5-bit address input
   .ADDRF(ADDRF), // Read port F 5-bit address input
   .ADDRG(ADDRG), // Read port G 5-bit address input
   .ADDRH(ADDRH), // Read/write port H 5-bit address input
   .DIA(DIA),     // RAM 2-bit data write input addressed by ADDRH,
                  //   read addressed by ADDRA
   .DIB(DIB),     // RAM 2-bit data write input addressed by ADDRH,
                  //   read addressed by ADDRB
   .DIC(DIC),     // RAM 2-bit data write input addressed by ADDRH,
                  //   read addressed by ADDRC
   .DID(DID),     // RAM 2-bit data write input addressed by ADDRH,
                  //   read addressed by ADDRD
   .DIE(DIE),     // RAM 2-bit data write input addressed by ADDRH,
                  //   read addressed by ADDRE
   .DIF(DIF),     // RAM 2-bit data write input addressed by ADDRH,
                  //   read addressed by ADDRF
   .DIG(DIG),     // RAM 2-bit data write input addressed by ADDRH,
                  //   read addressed by ADDRG
   .DIH(DIH),     // RAM 2-bit data write input addressed by ADDRH,
                  //   read addressed by ADDRH
   .WCLK(WCLK),   // Write clock input
   .WE(WE)        // Write enable input
);

// End of RAM32M16_inst instantiation

Related Information

  • UltraScale Architecture Configurable Logic Block User Guide (UG574)