TX_BITSLICE - 2023.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2023-05-17
Version
2023.1 English

Primitive: TX_BITSLICE for output using Native Mode

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: BITSLICE
  • Families: UltraScale, UltraScale+

Introduction

In native mode, the TX_BITSLICE contains serialization logic and a 512-tap output delay (ODELAY) that can be continuously adjusted for VT variation. The TX_BITSLICE contains serialization logic for 4:1 or 8:1 serialization.

Port Descriptions

Port Direction Width Function
CE Input 1 Clock enable for TX_BITSLICE ODELAY register clock.
CLK Input 1 Clock used to sample LOAD, CE, INC.
CNTVALUEIN<8:0> Input 9 Counter value from internal device logic for tap value to be loaded dynamically.
CNTVALUEOUT<8:0> Output 9 Counter value to going the internal device logic for monitoring tap value.
D<7:0> Input 8 Data from device logic
EN_VTC Input 1 Enable to keep stable delay over VT when set to HIGH. VT compensation disabled when set to LOW.
INC Input 1 Increment the current delay tap setting.
LOAD Input 1 Load the CNTVALUEIN tap setting.
O Output 1 Serialized output going to output buffer.
RST Input 1 Asynchronous assert, synchronous deassert for TX_BITSLICE OSERDES.
RST_DLY Input 1 Reset the internal DELAY value to DELAY_VALUE.
RX_BIT_CTRL_IN<39:0> Input 40 Input bus from BITSLICE_CONTROL.
RX_BIT_CTRL_OUT<39:0> Output 40 Output bus to BITSLICE_CONTROL.
T Input 1 Legacy T byte input from device logic.
TBYTE_IN Input 1 Byte group 3-state input from TX_BITSLICE_TRI.
T_OUT Output 1 Byte group 3-state output.
TX_BIT_CTRL_IN<39:0> Input 40 Input bus from BITSLICE_CONTROL.
TX_BIT_CTRL_OUT<39:0> Output 40 Output bus to BITSLICE_CONTROL.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog Yes

Available Attributes

Attribute Type Allowed Values Default Description
DATA_WIDTH DECIMAL 8, 4 8 Defines the parallel data input width. Legal values are 4 and 8.
DELAY_FORMAT STRING "TIME", "COUNT" "TIME" Sets the units of DELAY_VALUE of the TX_BITSLICE ODELAY. Use TIME when DELAY_TYPE is FIXED. Use COUNT when DELAY_TYPE is VARIABLE or VAR_LOAD.
  • "TIME": TX_BITSLICE ODELAY DELAY_VALUE is specified in ps.
  • "COUNT": TX_BITSLICE ODELAY DELAY_VALUE is specified in taps.
DELAY_TYPE STRING "FIXED", "VARIABLE", "VAR_LOAD" "FIXED" Sets the type of tap delay line.
  • "FIXED": Sets a static delay value.
  • "VARIABLE": Dynamically adjust (increment/decrement) delay value.
  • "VAR_LOAD": Dynamically loads tap values.
DELAY_VALUE DECIMAL 0 to 1250 0 Specifies the fixed delay in ps when using FIXED DELAY_TYPE. Specifies value upon reset when using VARIABLE or VAR_LOAD.
ENABLE_PRE_EMPHASIS STRING "FALSE", "TRUE" "FALSE" Used in conjunction with IOB to Enable the pre-emphasis.
INIT BINARY 1'b1, 1'b0 1'b1 Defines initial O value.
IS_CLK_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether the clock CLK pin is active-High or active-Low.
IS_RST_DLY_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether the reset RST_DLY pin is active-High or active-Low.
IS_RST_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether the reset RST pin is active-High or active-Low.
OUTPUT_PHASE_90 STRING "FALSE", "TRUE" "FALSE" Delays the output phase by 90-degrees.
REFCLK_FREQUENCY 1 significant digit FLOAT 200.0 to 2667.0 300.0 Specification of the reference clock frequency in MHz.
SIM_DEVICE STRING "7SERIES", "ULTRASCALE" "ULTRASCALE" Set the device version for simulation functionality.
TBYTE_CTL STRING "TBYTE_IN", "T" "TBYTE_IN" Select between T and TBYTE_IN inputs in OSERDES mode only.
UPDATE_MODE STRING "ASYNC", "MANUAL", "SYNC" "ASYNC"
  • "ASYNC": Updates are increments or decrements to the delay value independent of the data being received.
  • "SYNC": Updates require that input data transitions to synchronously update the delay with the data input edges.
  • "MANUAL": Updates take effect when both LOAD and CE are asserted after the LOAD and CNTVALUEIN signals are used to load the new CNTVALUE.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- TX_BITSLICE: TX_BITSLICE for output using Native Mode
--              UltraScale
-- Xilinx HDL Language Template, version 2023.1

TX_BITSLICE_inst : TX_BITSLICE
generic map (
   DATA_WIDTH => 8,                 -- Parallel data input width (4-8)
   DELAY_FORMAT => "TIME",          -- Units of the DELAY_VALUE (COUNT, TIME)
   DELAY_TYPE => "FIXED",           -- Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD)
   DELAY_VALUE => 0,                -- Output delay value setting
   ENABLE_PRE_EMPHASIS => "FALSE",  -- Enable the pre-emphasis
   INIT => '1',                     -- Defines initial O value
   IS_CLK_INVERTED => '0',          -- Optional inversion for CLK
   IS_RST_DLY_INVERTED => '0',      -- Optional inversion for RST_DLY
   IS_RST_INVERTED => '0',          -- Optional inversion for RST
   OUTPUT_PHASE_90 => "FALSE",      -- Delays the output phase by 90-degrees
   REFCLK_FREQUENCY => 300.0,       -- Specification of the reference clock frequency in MHz (200.0-2667.0)
   SIM_DEVICE => "ULTRASCALE_PLUS", -- Set the device version for simulation functionality (ULTRASCALE,
                                    -- ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)
   TBYTE_CTL => "TBYTE_IN",         -- Select between T and TBYTE_IN inputs
   UPDATE_MODE => "ASYNC"           -- Determines when updates to the delay will take effect (ASYNC, MANUAL,
                                    -- SYNC)
)
port map (
   CNTVALUEOUT => CNTVALUEOUT,         -- 9-bit output: Counter value to device logic
   O => O,                             -- 1-bit output: Serialized output going to output buffer
   RX_BIT_CTRL_OUT => RX_BIT_CTRL_OUT, -- 40-bit output: Output bus to BITSLICE_CONTROL
   TX_BIT_CTRL_OUT => TX_BIT_CTRL_OUT, -- 40-bit output: Output bus to BITSLICE_CONTROL
   T_OUT => T_OUT,                     -- 1-bit output: Byte group 3-state output
   CE => CE,                           -- 1-bit input: Clock enable for ODELAY
   CLK => CLK,                         -- 1-bit input: Clock used to sample LOAD, CE, INC
   CNTVALUEIN => CNTVALUEIN,           -- 9-bit input: Counter value from device logic
   D => D,                             -- 8-bit input: Data from device logic
   EN_VTC => EN_VTC,                   -- 1-bit input: Enable to keep stable delay over VT
   INC => INC,                         -- 1-bit input: Increment the current delay tap setting
   LOAD => LOAD,                       -- 1-bit input: Load the CNTVALUEIN tap setting
   RST => RST,                         -- 1-bit input: Asynchronous assert, synchronous deassert for
                                       -- TX_BITSLICE OSERDES

   RST_DLY => RST_DLY,                 -- 1-bit input: Reset the internal DELAY value to DELAY_VALUE
   RX_BIT_CTRL_IN => RX_BIT_CTRL_IN,   -- 40-bit input: Input bus from BITSLICE_CONTROL
   T => T,                             -- 1-bit input: Legacy T byte input from device logic
   TBYTE_IN => TBYTE_IN,               -- 1-bit input: Byte group 3-state input from TX_BITSLICE_TRI
   TX_BIT_CTRL_IN => TX_BIT_CTRL_IN    -- 40-bit input: Input bus from BITSLICE_CONTROL
);

-- End of TX_BITSLICE_inst instantiation

Verilog Instantiation Template


// TX_BITSLICE: TX_BITSLICE for output using Native Mode
//              UltraScale
// Xilinx HDL Language Template, version 2023.1

TX_BITSLICE #(
   .DATA_WIDTH(8),                 // Parallel data input width (4-8)
   .DELAY_FORMAT("TIME"),          // Units of the DELAY_VALUE (COUNT, TIME)
   .DELAY_TYPE("FIXED"),           // Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD)
   .DELAY_VALUE(0),                // Output delay value setting
   .ENABLE_PRE_EMPHASIS("FALSE"),  // Enable the pre-emphasis
   .INIT(1'b1),                    // Defines initial O value
   .IS_CLK_INVERTED(1'b0),         // Optional inversion for CLK
   .IS_RST_DLY_INVERTED(1'b0),     // Optional inversion for RST_DLY
   .IS_RST_INVERTED(1'b0),         // Optional inversion for RST
   .OUTPUT_PHASE_90("FALSE"),      // Delays the output phase by 90-degrees
   .REFCLK_FREQUENCY(300.0),       // Specification of the reference clock frequency in MHz (200.0-2667.0)
   .SIM_DEVICE("ULTRASCALE_PLUS"), // Set the device version for simulation functionality (ULTRASCALE,
                                   // ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)
   .TBYTE_CTL("TBYTE_IN"),         // Select between T and TBYTE_IN inputs
   .UPDATE_MODE("ASYNC")           // Determines when updates to the delay will take effect (ASYNC, MANUAL,
                                   // SYNC)
)
TX_BITSLICE_inst (
   .CNTVALUEOUT(CNTVALUEOUT),         // 9-bit output: Counter value to device logic
   .O(O),                             // 1-bit output: Serialized output going to output buffer
   .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT), // 40-bit output: Output bus to BITSLICE_CONTROL
   .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT), // 40-bit output: Output bus to BITSLICE_CONTROL
   .T_OUT(T_OUT),                     // 1-bit output: Byte group 3-state output
   .CE(CE),                           // 1-bit input: Clock enable for ODELAY
   .CLK(CLK),                         // 1-bit input: Clock used to sample LOAD, CE, INC
   .CNTVALUEIN(CNTVALUEIN),           // 9-bit input: Counter value from device logic
   .D(D),                             // 8-bit input: Data from device logic
   .EN_VTC(EN_VTC),                   // 1-bit input: Enable to keep stable delay over VT
   .INC(INC),                         // 1-bit input: Increment the current delay tap setting
   .LOAD(LOAD),                       // 1-bit input: Load the CNTVALUEIN tap setting
   .RST(RST),                         // 1-bit input: Asynchronous assert, synchronous deassert for
                                      // TX_BITSLICE OSERDES

   .RST_DLY(RST_DLY),                 // 1-bit input: Reset the internal DELAY value to DELAY_VALUE
   .RX_BIT_CTRL_IN(RX_BIT_CTRL_IN),   // 40-bit input: Input bus from BITSLICE_CONTROL
   .T(T),                             // 1-bit input: Legacy T byte input from device logic
   .TBYTE_IN(TBYTE_IN),               // 1-bit input: Byte group 3-state input from TX_BITSLICE_TRI
   .TX_BIT_CTRL_IN(TX_BIT_CTRL_IN)    // 40-bit input: Input bus from BITSLICE_CONTROL
);

// End of TX_BITSLICE_inst instantiation

Related Information

  • UltraScale Architecture SelectIO Resources User Guide (UG571)