TX_BITSLICE_TRI - 2023.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2023-05-17
Version
2023.1 English

Primitive: TX_BITSLICE_TRI for tristate using Native Mode

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: BITSLICE
  • Families: UltraScale, UltraScale+

Introduction

In native mode, the TX_BITSLICE_TRI provides the ability to tristate bitslices within a nibble. The TX_BITSLICE_TRI also contains a 512-tap output delay element (ODELAY) with a calibrated tap resolution.

Port Descriptions

Port Direction Width Function
BIT_CTRL_IN<39:0> Input 40 Input bus from BITSLICE_CONTROL.
BIT_CTRL_OUT<39:0> Output 40 Output bus to BITSLICE_CONTROL.
CE Input 1 Active-High enable increment/decrement input.
CLK Input 1 Clock input.
CNTVALUEIN<8:0> Input 9 Counter value from device logic for dynamically loadable tap value input.
CNTVALUEOUT<8:0> Output 9 Counter value to going the internal device logic for monitoring tap value.
EN_VTC Input 1 Enable to keep stable delay over VT when set to HIGH. VT compensation disabled when set to LOW.
INC Input 1 Increment the current delay tap setting.
LOAD Input 1 Load the CNTVALUEIN tap setting.
RST Input 1 Asynchronous assert, synchronous deassert.
RST_DLY Input 1 Reset the internal DELAY value to DELAY_VALUE.
TRI_OUT Output 1 Output to the TBYTE_IN pins of the bitslices.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog Yes

Available Attributes

Attribute Type Allowed Values Default Description
DATA_WIDTH DECIMAL 8, 4 8 Defines the parallel data input width. Legal values are 4 and 8.
DELAY_FORMAT STRING "TIME", "COUNT" "TIME" Sets the units of DELAY_VALUE of the TX_BITSLICE_TRI ODELAY. Use TIME when DELAY_TYPE is FIXED. Use COUNT when DELAY_TYPE is VARIABLE or VAR_LOAD.
  • "TIME": TX_BITSLICE_TRI ODELAY DELAY_VALUE is specified in ps.
  • "COUNT": TX_BITSLICE_TRI ODELAY DELAY_VALUE is specified in taps.
DELAY_TYPE STRING "FIXED", "VARIABLE", "VAR_LOAD" "FIXED" Sets the type of tap delay line.
  • "FIXED": Sets a static delay value.
  • "VARIABLE": Dynamically adjust (increment/decrement) delay value.
  • "VAR_LOAD": Dynamically loads tap values.
DELAY_VALUE DECIMAL 0 to 1250 0 Specifies the fixed delay in ps when using FIXED DELAY_TYPE. Specifies value upon reset when using VARIABLE or VAR_LOAD.
INIT BINARY 1'b1, 1'b0 1'b1 Defines initial O value.
IS_CLK_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether the clock CLK pin is active-High or active-Low.
IS_RST_DLY_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether the reset RST_DLY pin is active-High or active-Low.
IS_RST_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether the reset RST pin is active-High or active-Low.
OUTPUT_PHASE_90 STRING "FALSE", "TRUE" "FALSE" Delays the output phase by 90-degrees.
REFCLK_FREQUENCY 1 significant digit FLOAT 200.0 to 2667.0 300.0 Specification of the reference clock frequency in MHz.
SIM_DEVICE STRING "7SERIES", "ULTRASCALE" "ULTRASCALE" Set the device version for simulation functionality.
UPDATE_MODE STRING "ASYNC", "MANUAL", "SYNC" "ASYNC"
  • "ASYNC": Updates are increments or decrements to the delay value independent of the data being received.
  • "SYNC": Updates require that input data transitions to synchronously update the delay with the data input edges.
  • "MANUAL": Updates take effect when both LOAD and CE are asserted after the LOAD and CNTVALUEIN signals are used to load the new CNTVALUE.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- TX_BITSLICE_TRI: TX_BITSLICE_TRI for tristate using Native Mode
--                  UltraScale
-- Xilinx HDL Language Template, version 2023.1

TX_BITSLICE_TRI_inst : TX_BITSLICE_TRI
generic map (
   DATA_WIDTH => 8,                 -- Parallel data input width (4-8)
   DELAY_FORMAT => "TIME",          -- Units of the DELAY_VALUE (COUNT, TIME)
   DELAY_TYPE => "FIXED",           -- Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD)
   DELAY_VALUE => 0,                -- Output delay value setting
   INIT => '1',                     -- Defines initial O value
   IS_CLK_INVERTED => '0',          -- Optional inversion for CLK
   IS_RST_DLY_INVERTED => '0',      -- Optional inversion for RST_DLY
   IS_RST_INVERTED => '0',          -- Optional inversion for RST
   OUTPUT_PHASE_90 => "FALSE",      -- Delays the output phase by 90-degrees
   REFCLK_FREQUENCY => 300.0,       -- Specification of the reference clock frequency in MHz (200.0-2667.0)
   SIM_DEVICE => "ULTRASCALE_PLUS", -- Set the device version for simulation functionality (ULTRASCALE,
                                    -- ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)
   UPDATE_MODE => "ASYNC"           -- Determines when updates to the delay will take effect (ASYNC, MANUAL,
                                    -- SYNC)
)
port map (
   BIT_CTRL_OUT => BIT_CTRL_OUT, -- 40-bit output: Output bus to BITSLICE_CONTROL
   CNTVALUEOUT => CNTVALUEOUT,   -- 9-bit output: Counter value to device logic
   TRI_OUT => TRI_OUT,           -- 1-bit output: Output to the TBYTE_IN pins of the bitslices
   BIT_CTRL_IN => BIT_CTRL_IN,   -- 40-bit input: Input bus from BITSLICE_CONTROL
   CE => CE,                     -- 1-bit input: Active-High enable increment/decrement input
   CLK => CLK,                   -- 1-bit input: Clock input
   CNTVALUEIN => CNTVALUEIN,     -- 9-bit input: Counter value input
   EN_VTC => EN_VTC,             -- 1-bit input: Enable to keep stable delay over VT
   INC => INC,                   -- 1-bit input: Increment the current delay tap setting
   LOAD => LOAD,                 -- 1-bit input: Load the CNTVALUEIN tap setting
   RST => RST,                   -- 1-bit input: Asynchronous assert, synchronous deassert
   RST_DLY => RST_DLY            -- 1-bit input: Reset the internal DELAY value to DELAY_VALUE
);

-- End of TX_BITSLICE_TRI_inst instantiation

Verilog Instantiation Template


// TX_BITSLICE_TRI: TX_BITSLICE_TRI for tristate using Native Mode
//                  UltraScale
// Xilinx HDL Language Template, version 2023.1

TX_BITSLICE_TRI #(
   .DATA_WIDTH(8),                 // Parallel data input width (4-8)
   .DELAY_FORMAT("TIME"),          // Units of the DELAY_VALUE (COUNT, TIME)
   .DELAY_TYPE("FIXED"),           // Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD)
   .DELAY_VALUE(0),                // Output delay value setting
   .INIT(1'b1),                    // Defines initial O value
   .IS_CLK_INVERTED(1'b0),         // Optional inversion for CLK
   .IS_RST_DLY_INVERTED(1'b0),     // Optional inversion for RST_DLY
   .IS_RST_INVERTED(1'b0),         // Optional inversion for RST
   .OUTPUT_PHASE_90("FALSE"),      // Delays the output phase by 90-degrees
   .REFCLK_FREQUENCY(300.0),       // Specification of the reference clock frequency in MHz (200.0-2667.0)
   .SIM_DEVICE("ULTRASCALE_PLUS"), // Set the device version for simulation functionality (ULTRASCALE,
                                   // ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)
   .UPDATE_MODE("ASYNC")           // Determines when updates to the delay will take effect (ASYNC, MANUAL,
                                   // SYNC)
)
TX_BITSLICE_TRI_inst (
   .BIT_CTRL_OUT(BIT_CTRL_OUT), // 40-bit output: Output bus to BITSLICE_CONTROL
   .CNTVALUEOUT(CNTVALUEOUT),   // 9-bit output: Counter value to device logic
   .TRI_OUT(TRI_OUT),           // 1-bit output: Output to the TBYTE_IN pins of the bitslices
   .BIT_CTRL_IN(BIT_CTRL_IN),   // 40-bit input: Input bus from BITSLICE_CONTROL
   .CE(CE),                     // 1-bit input: Active-High enable increment/decrement input
   .CLK(CLK),                   // 1-bit input: Clock input
   .CNTVALUEIN(CNTVALUEIN),     // 9-bit input: Counter value input
   .EN_VTC(EN_VTC),             // 1-bit input: Enable to keep stable delay over VT
   .INC(INC),                   // 1-bit input: Increment the current delay tap setting
   .LOAD(LOAD),                 // 1-bit input: Load the CNTVALUEIN tap setting
   .RST(RST),                   // 1-bit input: Asynchronous assert, synchronous deassert
   .RST_DLY(RST_DLY)            // 1-bit input: Reset the internal DELAY value to DELAY_VALUE
);

// End of TX_BITSLICE_TRI_inst instantiation

Related Information

  • UltraScale Architecture SelectIO Resources User Guide (UG571)