Block RAM and UltraRAM used in designs from previous architectures are automatically migrated by inferring the appropriate Versal ACAP block. RTL instantiations are also automatically migrated. If certain block RAM and UltraRAM configurations are not supported in Versal ACAP, a critical warning message is issued and the instance is converted to a black box element. The design must be changed to adhere to the supported configurations for Versal ACAP. Xilinx recommends that you examine the configuration settings after design migration to ensure the correct defaults and settings were automatically selected. Xilinx recommends using Xilinx parameterizable macros (XPMs) to infer FIFOs and other memories. Built-in FIFOs are not supported in Versal ACAP. In the Vivado IP integrator, the Embedded Memory Generator and Embedded FIFO Generator replace the Block Memory Generator and FIFO Generator IP. The migration for the Block Memory Generator and FIFO Generator IP is not automatic. For detailed architectural differences, see the Versal ACAP Memory Resources Architecture Manual (AM007).
Some Versal ACAPs include accelerator RAM, an additional 4 MB of on-chip memory with ECC located outside of the PS. This memory provides direct access from the RPU via a 128-bit AXI interface and can also be accessed from the PL through two 256-bit AXI interfaces. The memory is divided into three banks supporting concurrent read or write accesses from the PL and RPU to different banks. For details on the PS RAM and accelerator RAM (XRAM), see the Versal ACAP Technical Reference Manual (AM011).
Some Versal devices contain an array of AI Engine tiles on the north edge of the device. The AI Engine array is a two dimensional array of AI Engine tiles that each contain: an AI Engine, a high-performance VLIW vector (SIMD) processor; integrated data memory; and interconnects for streaming, configuration, and debug.
Within each AI Engine is a dedicated, single-port, 16 KB program memory 128-bit wide and 1k deep. The program memory supports instruction compression and has ECC protection and reporting.
Separate from the AI Engine, each AI Engine tile contains 32 KB of data memory for AI Engine and divided into eight single-port banks. For more details about RAMs dedicated to the AIE arrays, see Versal ACAP AI Engine Architecture Manual (AM009).