Accessing the Link Partner - 3.0 English

DisplayPort 1.4 TX Subsystem Product Guide (PG299)

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3.0 English

The DisplayPort 1.4 TX Subsystem core is configured through the AXI4-Lite host interface. The host processor interface uses the DisplayPort AUX Channel to read the register space of the attached Sink device and determines the capabilities of the link. Accessing DPCD and EDID information from the Sink is done by writing and reading from register space 0x100 through 0x144. For information on the DPCD register space, see the VESA DisplayPort Standard v1.4 (VESA website).

Before any AUX channel operation can be completed, you must first set the proper clock divider value in 0x10C. This must be done only one time after a reset. The value held in this register should be equal to the frequency of s_axi_aclk. So, if s_axi_aclk runs at 135 MHz, the value of this register should be 135 ('h87). This register is required to apply a proper divide function for the AUX channel sample clock, which must operate at 1 MHz.

The act of writing to the AUX_COMMAND initiates the AUX event. Once an AUX request transaction is started, the host should not write to any of the control registers until the REPLY_RECEIVED bit is set to 1, indicating that the Sink has returned a response.