Polynomial used is,
f(x) = x16 + x15 + x2 + 1
Implementation is done as mentioned in the appendix of DP 1.4a specification except for the fact that there is an extra “init” input which takes the result of the CRC module from the previous clock cycle. In DP 1.4a specification, there is no separate input for previous clock’s CRC output. Instead it is denoted directly with the name of the output (which is ‘d’) of CRC module. The value of the per component’s CRC module’s output (‘dout’ in the example below) when VSYNC is detected is considered as the final calculated CRC value of specific component in that frame.
- Special case for YCbCr 422 mode in 1PPC mode
- For RGB video format, calculation of CRC per component is straight forward, but for YCbCr 422 mode, VESA recommends calculating CRC for each of the component namely Y, Cb and Cr. Hence there will be a special case of handling the data when it is 1PPC mode. This is because on Vid_In_AXIS_tdata, Cb and Cr alternate on the same most significant part of the data on every clock cycle in 1PPC mode and care is taken such that the same part of the data is routed to CRC module handling ‘Cb’ on one clock and to the CRC module handling ‘Cr’ on another clock.
- In this mode, for each of the ‘Cb’ and ‘Cr’ components, same data (din and init) will be held for 2 clock cycles at their respective CRC module’s inputs since there will be only one “Cb” component and only one “Cr” component per 2 clock cycles in 1 PPC mode.
- Block diagram of per component CRC calculator in 1PPC mode
- Here, “din” is loaded on every clock cycle, with
data corresponding to a component of each pixel.Figure 1. CRC calculator in 1PPC mode
- Block diagram of per component CRC calculator in 2PPC mode
- Here, “din1” and “din2” are loaded on every
clock cycle, with data corresponding to a component of two
consecutive pixels received in same clock (since 2 PPC
mode).Figure 2. CRC calculator in 2PPC mode