Physical Layout - 3.0 English

DisplayPort 1.4 TX Subsystem Product Guide (PG299)

Document ID
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3.0 English

When designing for the PCB, for pin outputs to the PCB from the PHY, refer to Video PHY Controller LogiCORE IP Product Guide (PG230). This section discusses the pin outputs from the subsystem and external IC/PCB considerations.

Note: Schematics and an example FMC card are available for purchase from Tokyo Electron Device Ltd.


The following pins will need to be driven through a level shifter, such as the SN74AVC4T774, followed by a line driver, such as the SN64MLVD2020A, and then an RC circuit to meet the DisplayPort standard requirements. See the DisplayPort standard for more information on switching requirements.

  • aux_tx_data_out
  • aux_tx_data_in
  • aux_tx_data_en_out_n
  • tx_hpd

The following pins are detailed in Video PHY Controller LogiCORE IP Product Guide (PG230), but Xilinx recommends sending these through a redriver, such as the SN65DP141, to simplify compliance testing.

Note: This is not a requirement to use the core, but doing so removes the need to adjust the transceiver settings during compliance.
  • phy_txn_out[x:0]
  • phy_txp_out[x:0]

For more information on schematic availability, refer to AR75465.

For all designs, reference the PCB design user guide and checklist. For UltraScale architectures, refer to UltraScale Architecture PCB Design User Guide (UG583) and UltraScale+ FPGAs and Zynq Ultrascale+ Devices Schematic Review Checklist (XTP427).