This section describes the link clock (
rx_lnk_clk), video clock (
rx_vid_clk), and Video Bridge to AXI4-Stream
master interface clock. When the AXI4 stream interface is selected for DP RX, the output clock
of Video to AXI4-stream bridge that is
should be selected such that it is greater than or equal to
rx_lnk_clk is a link
clock input to the DisplayPort 1.4 RX Subsystem generated by the Video PHY
hdcp_ext_clk input can
be driven from external MMCM or BUFGCDIV where it has a frequency requirement of
The following table shows the clock ranges.
|Clock Domain||Min (MHz)||Max (MHz)||Description|
|s_axi_aclk||25||135||Host processor clock|
The core uses six clock domains:
rxoutclkfrom the Video PHY is connected to the RX subsystem link clock. Most of the core operates in link clock domain. This domain is based on the
lnk_clk_p/nreference clock for the transceivers. The link rate switching is handled by a DRP state machine in the core PHY later. When the lanes are running at 2.7 Gb/s,
lnk_clkoperates at 135 MHz. When the lanes are running at 1.62 Gb/s,
lnk_clkoperates at 81 MHz. When the lanes are running at 5.4 Gb/s,
lnk_clkoperates at 270 MHz. When the lanes are running at 8.1 Gb/s,
lnk_clkoperates at 405 MHz.
In the DisplayPort Sink core,
lnk_clkis derived from the recovered clock from the transceiver. When the cable is disconnected this clock becomes unstable.Note:
link_rate/20, when GT-Data width is 16-bit.
- This is the primary user interface clock. Frequency of this clock is
dependent on whether "frame buffer" is being used in the design or not as well as if the
interface is AXI or Native Mode. If an inaccurate clock is used, the DisplayPort FIFO can
overflow or underflow causing data corruption.
- AXI Mode with a Frame Buffer
- With a frame buffer,
rx_vid_clkcan run up to 300 MHz and must be at least equal to the (pixel clock/Configured PPC).
- This is the Xilinx® implemented solution as it does not require any external clock management.
- Native Mode or AXI Mode without a Frame Buffer
- For non-frame buffer designs, the DisplayPort RX core requires the generation of a video
stream using the M and N values within the Main Stream Attributes to reconstruct an
accurate stream clock. The DisplayPort RX core places this information on dedicated signals and
provides an update flag to signal a change in these values. The following figure
shows how to use the M and N values from the core to generate a clock. For more
details, see the
Standard (VESA website). Recommended: The Xilinx® MMCM is not accurate enough to be used to regenerate the necessary clock for non-frame buffer design. You need to use an external PLL that meets the requirements of the DisplayPort standard. For more details, see the VESA DisplayPort Standard (VESA website).Figure 1. Receiver Clock Generation
- This is the processor domain. It has been tested to run as fast as 135
MHz. The AUX clock domain is derived from this domain, but requires no additional
s_axi_aclkclock is connected to a free-running clock input.
gtwiz_reset_clk_freerun_inis required by the reset controller helper block to reset the transceiver primitives. A new GUI parameter is added for AXI_Frequency, when the DisplayPort IP is targeted to UltraScale FPGA.
- This is the audio interface clock. The frequency will be equal to 512 × audio sample rate.
- This clock is used by the source audio streaming interface. This clock should be = 512 × audio sample rate.
- This clock is used by the sink audio streaming interface. This clock should be = 512 × audio sample rate.
For more information on clocking, see the Video PHY Controller LogiCORE IP Product Guide (PG230).