DPCD Configuration Space - 3.0 English

DisplayPort 1.4 RX Subsystem Product Guide (PG300)

Document ID
PG300
Release Date
2022-05-04
Version
3.0 English

For detailed descriptions of these registers, see the VESA DisplayPort Standard (VESA website) standard.

Table 1. DPCD Configuration Space
Offset Access Type Description
0x400 RO DPCD_LINK_BW_SET. Link bandwidth setting.

[7:0] - Set to 0x0A when the link is configured for 2.7 Gb/s or 0x06 when configured for 1.62 Gb/s or 0x14 when link is configured for 5.4 Gb/s.

0x404 RO

DPCD_LANE_COUNT_SET. Number of lanes enabled by the transmitter.

[4:0] - Contains the number of lanes that are currently enabled by the attached transmitter. Valid values fall in the range of 1-4.

0x408 RO DPCD_ENHANCED_FRAME_EN. Indicates that the transmitter has enabled the enhanced framing symbol mode.

[0] - Set to 1 when enhanced framing mode is enabled.

0x40C RO

DPCD_TRAINING_PATTERN_SET. Current value of the training pattern registers.

[1:0] - TRAINING_PATTERN_SET: Set the link training pattern according to the 2-bit code:
  • 000 = Training not in progress
  • 001 = Training pattern 1
  • 010 = Training pattern 2
  • 011 = Training pattern 3
  • 111 = Training pattern 4
0x410 RO

DPCD_LINK_QUALITY_PATTERN_SET. Current value of the link quality pattern field of the DPCD training pattern register.

[1:0] - transmitter is sending the link quality pattern:
  • 00 = Link quality test pattern not transmitted
  • 01 = D10.2 test pattern (unscrambled) transmitted
  • 10 = Symbol Error Rate measurement pattern
  • 11 = PRBS7 transmitted
0x414 RO

DPCD_RECOVERED_CLOCK_OUT_EN. Value of the output clock enable field of the DPCD training pattern register.

[0] - Set to 1 to output the recovered receiver clock on the test port.

0x418 RO

DPCD_SCRAMBLING_DISABLE. Value of the scrambling disable field of the DPCD training pattern register. By default, scrambling is disabled.

[0] - Set to 1 when the transmitter has disabled the scrambler and transmits all symbols.

0x41C RO

DPCD_SYMBOL_ERROR_COUNT_SELECT. Current value of the symbol error count select field of the DPCD training pattern register.

[1:0] - SYMBOL_ERROR_COUNT_SEL:
  • 00 = Disparity error and illegal symbol error
  • 01 = Disparity error
  • 10 = Illegal symbol error
  • 11 = Reserved
0x420 RO

DPCD_TRAINING_LANE_0_SET. Used by the transmitter during link training to configure the receiver PHY for lane 0.

[5] - MAX_PRE-EMPHASIS_REACHED: Set to 1 when the maximum pre-emphasis setting is reached.

[4:3] - PRE-EMPHASIS_SET
  • 00 = Training Pattern 2 without pre-emphasis
  • 01 = Training Pattern 2 with pre-emphasis level 1
  • 10 = Training Pattern 2 with pre-emphasis level 2
  • 11 = Training Pattern 2 with pre-emphasis level 3

[2] - MAX_SWING_REACHED: Set to 1 when the maximum driven current setting is reached.

[1:0] - VOLTAGE_SWING_SET
  • 00 = Training Pattern 1 with voltage swing level 0
  • 01 = Training Pattern 1 with voltage swing level 1
  • 10 = Training Pattern 1 with voltage swing level 2
  • 11 = Training Pattern 1 with voltage swing level 3
0x424 RO DPCD_TRAINING_LANE_1_SET. Used by the transmitter during link training to configure the receiver PHY for lane 0. The fields of this register are identical to DPCD_TRAINING_LANE_0_SET.
0x428 RO DPCD_TRAINING_LANE_2_SET. Used by the transmitter during link training to configure the receiver PHY for lane 0. The fields of this register are identical to DPCD_TRAINING_LANE_0_SET.
0x42C RO DPCD_TRAINING_LANE_3_SET. Used by the transmitter during link training to configure the receiver PHY for lane 0. The fields of this register are identical to DPCD_TRAINING_LANE_0_SET.
0x430 RO

DPCD_DOWNSPREAD_CONTROL. The transmitter uses this bit to inform the receiver core that downspreading has been enabled.

[0] - SPREAD_AMP: Set to 1 for 0.5% spreading or 0 for none.

0x434 RO

DPCD_MAIN_LINK_CHANNEL_CODING_SET. 8B/10B encoding can be disabled by the transmitter through this register bit.

[0] - Set to 0 to disable 8B/10B channel coding. The default is 1.

0x438 RO

PCD_SET_POWER_STATE. Power state requested by the source core. On reset, power state is set to power down mode.

[1:0] - Requested power state
  • 00 = Reserved
  • 01 = state D0, normal operation
  • 10 = state D3, power down mode
  • 11 = Reserved
0x43C RO

DPCD_LANE01_STATUS. Value of the lane 0 and lane 1 training status registers.

Write-Only Access

[31] - Override Lane Set Registers

[27:26] - Override Pre-Emphasis Level

[25:24] - Override Voltage Level

Read-Only Access

[15:14] - Lane 1 Adjust Pre-Emphasis Value

[13:12] - Lane 1 Adjust Voltage Value

[11:10] - Lane 0 Adjust Pre-Emphasis Value

[9:8] - Lane 0 Adjust Voltage Value

[6] - LANE_1_SYMBOL_LOCKED. Set to 1 when, the 8B10B pattern is locked and TP2/3 pattern is locked on LANE_1.

[5] - LANE_1_CHANNEL_EQ_DONE. Set to 1, when the lane alignment is done on LANE_1.

[4] - LANE_1_CLOCK_RECOVERY_DONE. Set to 1, when D10.2 symbol is locked on LANE_1.

[2] - LANE_0_SYMBOL_LOCKED. Set to 1 when, the 8B10B pattern is locked and TP2/3 pattern is locked on LANE_0.

[1] - LANE_0_CHANNEL_EQ_DONE. Set to 1, when the lane alignment is done on LANE_0.

[0] - LANE_0_CLOCK_RECOVERY_DONE. Set to 1, when D10.2 symbol is locked on LANE_0.

0x440 RO

DPCD_LANE23_STATUS. Value of the lane 2 and lane 3 training status registers.

Read-Only Access

[15:14] - Lane 3 Adjust Pre-Emphasis Value

[13:12] - Lane 3 Adjust Voltage Value

[11:10] - Lane 2 Adjust Pre-Emphasis Value

[9:8] - Lane 2 Adjust Voltage Value

[6] - LANE_3_SYMBOL_LOCKED. Set to 1 when, the 8B10B pattern is locked and TP2/3 pattern is locked on LANE_3.

[5] - LANE_3_CHANNEL_EQ_DONE. Set to 1, when the lane alignment is done on LANE_3.

[4] - LANE_3_CLOCK_RECOVERY_DONE. Set to 1, when D10.2 symbol is locked on LANE_3.

[2] - LANE_2_SYMBOL_LOCKED. Set to 1 when, the 8B10B pattern is locked and TP2/3 pattern is locked on LANE_2.

[1] - LANE_2_CHANNEL_EQ_DONE. Set to 1, when the lane alignment is done on LANE_2.

[0] - LANE_2_CLOCK_RECOVERY_DONE. Set to 1, when D10.2 symbol is locked on LANE_2.

0x444 RO

SOURCE_OUI_VALUE. Value of the Organizationally Unique Identifier (OUI) as written by the transmitter via the DPCD register AUX transaction.

[23:0] - Contains the value of the OUI set by the transmitter. This value might be used by the host policy maker to enable special functions across the link.

0x448 RC/RO SYM_ERR_CNT01. Reports symbol error counter of lanes 0 and 1. The lane 0 and lane 1 error counts are cleared when this register is read.

[31] - Lane 1 error count valid

[30:16] - Lane 1 error count

[15] - Lane 0 error count valid

[14:0] - Lane 0 error count

0x44C RC

SYM_ERR_CNT23. Reports symbol error counter of lanes 2 and 3. The lane 2 and lane 3 error counts are cleared when this register is read.

[31] - Lane 3 error count valid

[30:16] - Lane 3 error count

[15] - Lane 2 error count valid

[14:0] - Lane 2 error count

0x454 RO

DPCD Value written by DP Source

[31:0] - {5’d0, Link_Qual_Lane3, 5’d0,Link_Qual_Lane2, 5’d0,Link_Qual_Lane2, 5’d0,Link_Qual_Lane0}

0x45C R/W

[31:16] - PRBS Error Counter - Lane 1 {Valid, 15-bit counter value}

[15:0] - PRBS Error Counter - Lane 0 {Valid, 15-bit counter value}

0x460 R/W

[31:16] - PRBS Error Counter - Lane 3 {Valid, 15-bit counter value}

[15:0] - PRBS Error Counter - Lane 2 {Valid, 15-bit counter value}