When designing for the PCB, for pin outputs to the PCB from the PHY, refer to Video PHY Controller LogiCORE IP Product Guide (PG230). This section discusses the I/O pins of the subsystem and external IC/PCB considerations.
I/O Pins
-
aux_rx_data_out -
aux_rx_data_en_out_n -
aux_rx_data_in -
ext_iic -
rx_hpd
The aux_* and hpd signals are sent through a level shifter, such as the
SN74AVC4T774, followed by a line driver, such as the SN64MLVD2020A and then an RC
circuit before the rx_out and rx_in signals are connected to SBU1 and SBU2 (P/N) of
the MCDP6000. The ext_iic lines are connected to
the SCL/SCA lines of the MDCP6000.
PHY Pins
The following pins are detailed in Video PHY Controller LogiCORE IP Product Guide (PG230).
-
link_rx_lane_n[x:0] -
link_rx_lane_p[x:0]
The following DisplayPort link pins are connected to the MCDP6000 RX and TX pins. For more details, see the MCDP6000 documentation.
-
link_rx_lane_n[0]toRX1n -
link_rx_lane_n[1]toTX1n -
link_rx_lane_n[2]toTX2n -
link_rx_lane_n[3]toRX2n
For more information on schematic availability, refer to AR75465.
For all designs, reference the PCB design user guide and checklist. For UltraScale architectures, refer to UltraScale Architecture PCB Design User Guide (UG583) and UltraScale+ FPGAs and Zynq Ultrascale+ Devices Schematic Review Checklist (XTP427).