AXI4-Stream C2H Write Cmp Interface

AXI4-Stream C2H Write Cmp Interface - 3.0 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID

PG347

Release Date

2022-06-15

Version

3.0 English

Table 1. AXI-ST C2H Write Cmp Interface Descriptions
Port Name	I/O	Description
dma0_axis_c2h_dmawr_cmp	O	This signal is asserted when the last data payload write request of the packet gets the write completion. It is one pulse per packet.