DMA Clock
QDMA and AXI Bridge runs on clock that is provide by user. This is a
change from CPM4 (where the clock is provided by the IP). You must provide a clock
dma<n>_intrfc_clk, which will be used by
the IP. All the input ports and output ports will be driver or loaded using this
clock. Because this is a independent clock provided by the user there are some
restrictions on clock frequency based on the IP configurations, which are listed
below.
| Configuration Options | Frequency |
|---|---|
| Gen3x16 | 250 MHz |
| Gen4x8 | 250 MHz |
| Gen4x16 | 500 MHz |
| Gen5x8 | 500 MHz |
Input clock for IP configurations that interact with PL directly will have limitation based on timing closure. It is recommended not to go over 400MHz for any logic in PL. For example, AXI Stream interface or QDMA1 AXI4-MM interface can access PL directly, in these case user needs to be careful in choosing input clock frequency.
For QDMA1 AXI-MM interface there are two more clock inputs that you
must provide clocks, cpm_pl_axi0_clk and cpm_pl_axi1_clk.
PCIe Ref Clock
Each link partner device shares the same reference clock source. The following figures show a system using a 100 MHz reference clock. Even if the device is part of an embedded system, if the system uses commercial PCI Express® root complexes or switches along with typical motherboard clocking schemes, synchronous clocking should be used.
