- Make the connections between the IP cores as shown in following figure.
- Set
GT_REFCLK_D
,GT_PCIEA0_RX
,GT_PCIEA0_TX
,SYS_CLK0
, andCH0_DDR4_0
as primary ports. To do so:- Select pins
gt_refclk0
, andPCIE0_GT
of versal_cips_0,SYS_CLK0
andCH0_DDR4_0
of axi_noc_0 by pressing Ctrl+click. - Click the Make External (Ctrl + T) icon in the toolbar at the top of the canvas.
- Select pins
- Connect NoC/CIPS ports as shown in picture.
- Connect "pl0_ref_clk" from CIPS output to "dma0_intrfc_clk" CIPS Input (DMA input clock)
- Add a Constant IP, and configure the IP to generate a constant
value of logic 1 and connect to
dma0_intrfc_resetn
input reset port..