Next, add signal connections between
the IP in the Vivado IP integrator.
- Make the connections between the IP cores as shown in following figure.
- Set
GT_REFCLK_D
,GT_PCIEA0_RX
,GT_PCIEA0_TX
,SYS_CLK0_IN
andCH0_DDR4_0
as primary ports. To do so:- Select pins
GT_REFCLK_D
,GT_PCIEA0_RX
andGT_PCIEA0_TX
of versal_cips_0,SYS_CLK0_IN
of clk_gen_sim_0, andCH0_DDR4_0
of axi_noc_0 by pressing Ctrl+click. - Click the Make External (Ctrl + T) icon in the toolbar at the top of the canvas.
- Select pins