Next you will add and
configure a Network on Chip (NoC) IP core for the DDR connection.
- Right-click the block design canvas and from the context menu select Add IP.
- The IP catalog pops up. In the Search field type
AXI NoCto filter a list of IP. - From the filtered list, double-click the AXI NoC IP core to instantiate the IP on the
block design canvas.
Customize the IP as follows:
- In the General tab, set the following options:
- Number of AXI Slave Interfaces: 2.
- Number of AXI Master Interfaces: 0.
- Number of AXI Clocks: 2.
The number of AXI clocks is set to two because there are two clocks needed for the AXI Slave input, and none needed for AXI Master output.
- Memory Controller: Single Memory Controller.
- Number of Memory Controller Port: 4.
- All others options use the default settings.
- In the Inputs tab, set the following options.
First row (for S00_AXI):
- Connected To: PS PCIe.
- Clock: aclk0 (input clock).
- All other options use default settings.
Second row (for S01_AXI):
- Connected To: PS PCIe.
- Clock: aclk1 (input clock).
- All other options use default settings.
- In the Connectivity tab, set the NoC connectivity as
follows:
- For S00_AXI, select the MC Port 0 checkbox.
- For S01_AXI, select the MC Port 0 checkbox.
- All others options use the default settings.
- In the DDR Basic tab, set the following options:
- Input System clock period (ps): 5000 (200.000 MHz).
- Select the Enable Internal Responder checkbox.
- All others options use the default settings.
Note: This is a sample configuration. Your DDR configuration and frequencies should be based on your design requirements. - In the DDR Memory tab, set the following options:
- Memory Device Type: Components.
- Memory Speed Grade: DDR4-3200AA(22-22-22).
- Base Component Width: x16.
- All others options use the default settings.
- Click OK to generate a NoC IP with DDR.