The Versal ACAP silicon has a hardened, centralized platform management controller (PMC) that provides a capability set to boot the device, monitor system activity, provide test and debug infrastructure, perform security core functions, and respond to error and safety events. The PMC allows for great flexibility in the timing, source, and mechanism in which a bitstream can be delivered and loaded to the device. This appendix focuses on the details of how to configure the hardware and software to enable a user to deliver a Stage 2 or reconfigurable partition bitstream across the PCIe link when using CPM to the PMC for delivery to the underlying device resources.
The PCI Express base specification places a hard
timing requirement on a component being able to begin link training 20ms after the end
of fundamental reset and its companion, the PCI Express card's
electromechanical specification, places a similar requirement on the minimum time before
deassertion of the PERST# signal of 100 ms after power is stable and
within operating limits. The sum of the two timing requirements (120 ms) places a hard
boundary on the lower operating limit that a Versal ACAP device
functioning as a PCIe component must be ready to link train after
power is applied to the system. A Versal ACAP is a complex device
with stringent power sequencing and boot operations and contains a large number of
hardware resources, making it impossible to meet this timing requirement when loading
the entirety of a large bitstream to the device. Fortunately, the Tandem PROM and Tandem
PCIe boot configurations built into the CPM IP and Vivado Design Suite allow for an easy method to generate bitstreams that
allow a Versal ACAP to meet the difficult timing requirement by
reorganizing and partitioning the bitstream components to put the CPM configuration
first. Tandem PROM does not require any intervention beyond setting the option in the
Vivado Design Suite CIPS IP customization GUI. Tandem PCIe is employed to split the full bitstream into two stages, with the
second stage being loaded across the PCIe link after enumeration has
occurred.
The dynamic function eXchange (DFX) feature supported by much of the Xilinx silicon portfolio and Vivado Design Suite allows for the reconfiguration of the modules within an active device. It gives system architects the flexibility to switch a portion of the design in and out depending on the system requirements, removing the need to multiplex multiple functions in a larger device, which saves on part cost, power and improves system up time. Taking advantage of the PCIe link with CPM for delivery of reconfigurable partition bitstream data to the PMC allows for high throughput and minimal design requirements and is simplified by provided software and drivers.