RESET Placements - 3.0 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-06-15
Version
3.0 English

Allowed placements are shown in the table below. Placements are selected in CIPS IP configuration GUI as part of PS PMC peripheral and I/O configuration selections.

Table 1. Allowed Reset Pin Placements
CPM5 PCIE Controller and Port Type RESET Pin Location Options
0: Endpoint, Switch Ports (Up/Down) PS MIO 18 (Default)
PMC MIO 24
PMC MIO 38
1: Endpoint, Switch Ports (Up/Down) PS MIO 19 (Default)
PS MIO 25
PS MIO 39
0: Root Port PS MIO 0 (Default)
PS MIO 0 – 25
PMC MIO 0 – 51
1: Root Port PS MIO 1 (Default)
PS MIO 0 – 25
PMC MIO 0 – 51