Output Clocks - 3.0 English

Control Interfaces and Processing System LogiCORE IP Product Guide (PG352)

Document ID
PG352
Release Date
2021-06-16
Version
3.0 English

This section displays the default/user selected peripheral clocks which are allowed to update the frequency. Also output clocks hold different domain PLLs.

PLLs in the PS and PMC are:
APLL
APU PLL which is in FPD domain
NPLL
NoC PLL which is in PMC domain
RPLL
RPU PLL which is in LPD domain
PPLL
PMC PLL which is in PMC domain

In the default mode (when the manual mode is turned off), the core automatically chooses the source PLLs and calculates the M (Multiplier) and D (Divisor) values, to ensure that the tool meets the requested frequency to the nearest possible value. The core might not achieve all the requested values, since each PLL caters to multiple peripherals. An internal algorithm creates the best possible solution based on the following conditions.

The algorithm chooses source PLL on its own and the rule is the PMC domain PPLL, NPLL can be used to source in LPD and FPD. The LPD domain RPU PLL can be used to source in and FPD, vice-versa is possible only by setting cross domain PLL parameter.

  • When Ethernet is enabled, the core tries to give the precedence to the solution which has the Ethernet frequency of 125 MHz. In manual mode divisors should be made in order to obtain either of 125/25/2.5 MHz.
  • When Ethernet is enabled and if there are multiple clocking solutions with the identical Ethernet frequency of 125 MHz, then the tool will take the precedence of the solution that will have the least possible total error (sum of requested frequencies-sum of actual frequencies) value of various peripherals.
  • The tool will also take the precedence of the solution with least possible total error value of various peripherals even when the Ethernet is disabled.
  • The tool will generate CAN clocks within 0.25 % tolerance and GEM clocks with +/- 100 ppm tolerance. If the tool unable to derive these with set of input clocks then it generates a DRC.
  • Tool will generate SDIO ref clock and SD DLL clocks as mentioned below.
    1. In auto mode fixed 200 MHz for SDIO0/1 and 1200 MHz for SD DLL.
    2. In manual mode DRC is provided if you are not using the same PLL for SD DLL and SDIO0/1 ref clock.
    3. In manual mode DRC is provided if SD DLL ref clock is not = 6 times SDIO0/1 ref clock.
Figure 1. Output Clocks

Enable Manual Clocking Mode

When you select this mode, different options are displayed. You can directly input the Source PLL, M and D values for various PLLs as well as individual peripheral clock divisor values enabling finer control. In Manual clocking mode, the default divisor values are given for input Ref clock frequency of 33.33 MHz. If you move to the manual mode with different ref clock frequency, then you will encounter DRC’s for divisor values which user need to resolve manually.

PMC Power Domain Clocks

Processor/Memory Clocks
Clock configuration for the HSM0, which is source for AIE PLL. HSM1 which is source for DDR PLL.
Peripherals/IO Clocks
Clock configuration for boot devices like OSPI, SD/eMMC and clocks for NPI, NoC.
Interconnect and Switch Clocks
Clock configuration for interconnects and switches in PMC domain.

Low Power Domain Clocks

Processor/Memory Clocks
Clock configuration for the CPU_R5 Processor.
Peripherals/IO Clocks
Clock configuration for low-speed peripheral devices.
Interconnect and Switch Clocks
Clock configuration for interconnects and switches in LPD domain.
System Debug Clocks
Clock configuration for debug modules DBG_LPD, DBG_TSTMP.

Full Power Domain Clocks

Processor/Memory Clocks
Clock configuration for APU, GPU, and DDR
System Debug Clocks
Clock configuration for debug modules: DBG_FPD
Interconnect and Switch Clocks
Clock configuration for interconnects and switches in FPD domain

PL Clocks

The Versal Control, Interfaces and Processing System provides four clocks to the PL. Versal CIPS IP core enables the configuration of these clocks to be used in the PL. The Versal CIPS core inserts a BUFG for each of the PL clocks. Also, PCW provide option to select IRO clock to enable and connect to PL peripherals.

You can use PMC domain PLL's in FPD and LPD but the reverse is not allowed because only forward path clocking is followed in CIPS.

Table 1. Output Clocks and their Descriptions
Output Clock Description
Source This is the source PLL for the corresponding peripheral
Requested Freq (MHz) This is the input frequency given to the corresponding peripheral
Divisor 0 Denotes the 6-bit programmable Divisor
Actual Freq (MHz) This is the actual frequency calculated by the Processor Configuration. The clocking algorithm works with multiple factors, peripherals, PLLs, and priorities. Therefore, in certain cases, the actual frequency might be different than the requested frequency.
Range (MHz) This is the minimum/maximum range of the frequency that the corresponding peripheral can work with. In this mode, you must configure the M and D values to achieve the desired frequency. When this mode is enabled, the values requested through the output mode will be overwritten.
Note: In order to modify the clock frequencies/divisors, the corresponding clock must be enabled.