In addition to the Video PHY Controller /HDMI GT Subsystem, HDMI Transmitter Subsystem and HDMI Receiver Subsystem core, the complete example design includes the following cores:
- MicroBlaze, Zynq, Zynq UltraScale+ MPSoC, or Versal ACAP
- MicroBlaze Debug Module (Only for MicroBlaze based processor subsystem)
- AXI Interconnect
- Local Memory Bus (LMB) (Only for MicroBlaze based processor subsystem)
- LMB BRAM Interface Controller (Only for MicroBlaze based processor subsystem)
- Block Memory Generator (Only for MicroBlaze based processor subsystem)
- Clocking Wizard
- Processor System Reset Module
- AXI UART Lite (Only for MicroBlaze based processor subsystem)
- AXI Interrupt Controller (INTC) (Only for MicroBlaze based processor subsystem)
- AXI IIC Bus Interface
- AXI GPIO
- Video Test Pattern Generator
- AXI4-Stream Register Slice
- Utility Buffer
- Utility Vector Logic
- AUD_PAT_GEN (Custom IP)
- HDMI_ACR_CTRL (Custom IP)
- HDCP_KEYMNGMT_BLK (Custom IP) Note: When a Custom IP is added to an IP integrator design as RTL reference module, the auto assigned address can be maximized to any of the available space. Therefore, if you unmap AUD_PAT_GEN, HDMI_ACR_CTRL or HDCP_KEYMNGMT_BLK for the Example design, after reassigning the address, you must set the address to a smaller range (for example, 64k).