Interrupts - 3.1 English

All interrupts generated by the HDMI 1.4/2.0 TX Subsystem are listed here:

1. HPD – Peripheral I/O to detect HDMI cable 5.0V signal
   1. Rising edge – If HPD disconnect interrupt has happened and HPD line is asserted for more than 10 ms.
   2. Falling edge – If HPD line is deasserted for more than 100 ms.
   3. Toggle - A pulse occurred on the HPD line with a pulse width between 50 and 99 ms.
2. Link Ready – Every time the PHY Controller is reconfigured, the link_clk is regenerated. An HDMI TX sub-core register bit (link status bit) reflects the change of link_clk status. . When stable link_clk is detected, it is set to 1. When link_clk becomes unstable, it is set to 0. The Link Ready is an interrupt to detect the change of the link status bit.
   1. Rising edge – Link is up
   2. Falling edge – Link is down
3. Vertical Sync – This is to reflect the change of HDMI TX sub-core vsync input signal in its video interface bus.
   1. Rising edge – Vertical Sync is detected
4. Video Bridge Unlocked - The AXI4-Stream to Video Out Bridge lost lock with the incoming AXI4 Video Stream.
5. HDCP1.4 Interrupt (only available when HDCP 1.4 is enabled in hardware)
6. HDCP 1.4 Timer Interrupt (only available when HDCP 1.4 is enabled in hardware)
7. HDCP 2.3 Timer Interrupt (only available when HDCP 2.3 is enabled in hardware)