The example design is built around the HDMI 1.4/2.0 Transmitter Subsystem (HDMI_TX_SS), the HDMI 1.4/2.0 Receiver Subsystem (HDMI_RX_SS) (Optional), and the Video PHY Controller (VPHY) /HDMI GT Subsystem core and leverages existing Xilinx IP cores to form the complete system. The following two figures are illustrations of the overall HDMI example design block diagram targeting various Xilinx evaluation kits.
The Video PHY Controller /HDMI GT Subsystem core has been configured for the HDMI application that allows transmission and reception (optional) of HDMI video/audio to and from the HDMI 2.0 daughter card or on-board HDMI 2.0 circuitry.
In pass-through mode, the Video PHY Controller /HDMI GT Subsystem core receives the high-speed serial TMDS stream, converts it to parallel data streams, forwards it to the HDMI_RX_SS core, which extracts the video and audio streams from the HDMI stream and converts it to separate AXI video and audio streams. The AXI video goes through the TPG core and the AXI audio goes through a customized audio generation block. The two AXI streams eventually reach the HDMI_TX_SS core, which converts the AXI video and audio streams back to an HDMI stream before being transmitted by the Video PHY Controller /HDMI GT Subsystem core as a high-speed serial data stream. The transition minimized differential signaling (TMDS) clock from the HDMI In interface is forwarded to the HDMI TX transceiver through the SI53xx clock generator in the HDMI 2.0 FMC card or on-board HDMI 2.0 circuitry.
In the RX-only mode, an external HDMI source is used to send video data, and the HDMI Example design receives and detects the video. You can check the video information from the UART menu.
High-level control of the system is provided by a simplified embedded processor subsystem containing I/O peripherals and processor support IP. A clock generator block and a processor system reset block supply clock and reset signals for the system, respectively. See the following two figures for block diagrams of the three types of processor subsystems supported by the HDMI example design flow.