Introduction - 3.1 English

HDMI 1.4/2.0 Receiver Subsystem Product Guide (PG236)

Document ID
PG236
Release Date
2020-12-11
Version
3.1 English

A high-level block diagram of the HDMI 1.4/2.0 RX Subsystem is shown in the following figure.

Figure 1. Subsystem Block Diagram

The HDMI 1.4/2.0 RX Subsystem is constructed on top of an HDMI RX core. Various supporting modules are added around the HDMI RX core with respect to your configuration. The HDMI RX core is designed to support native video interface, however many of the existing video processing IP cores are AXI4-Stream-based. It is a natural choice to add a converter module (Video In to AXI4-Stream) to enable the HDMI 1.4/2.0 RX Subsystem to output AXI4-Stream-based video. Doing this allows the HDMI 1.4/2.0 RX Subsystem to work seamlessly with other Xilinx video processing IP cores. The HDMI 1.4/2.0 RX Subsystem has a built-in capability to optionally support both HDCP 1.4 and HDCP 2.3 encryption. The HDMI 1.4/2.0 RX Subsystem has a built-in capability to optionally support both HDCP 1.4 and HDCP 2.3 decryption.

The HDMI 1.4/2.0 RX Subsystem supports the following types of video interface:

  • AXI4-Stream Video Interface
  • Native Video Interface
  • Native Video (Vectored Data Enable (DE)) Interface

The following figure shows the internal structure of the HDMI 1.4/2.0 RX Subsystem when AXI4-Stream is selected as the video interface. In this illustration, both HDCP 1.4 and HDCP 2.3 are selected and both Video over AXIS compliant NTSC/PAL Support and Video over AXIS compliant YUV420 Support are selected.

Figure 2. HDMI RX Subsystem Internal Structure in AXI4-Stream Video Interface Mode

The HDMI 1.4/2.0 RX Subsystem also provides an option to support a native video interface by constructing the subsystem without the Video In to AXI4-Stream bridging module. Some applications require support of customized resolutions, which are not divisible by the PPC setting (4 or 2). Therefore, the HDMI 1.4/2.0 RX Subsystem also provides a native video (Vectored DE) interface option to enable this application. When native video interface (with or without Vectored DE) is selected, the HDMI 1.4/2.0 RX Subsystem outputs native video to its own video devices. In native video mode, the HDMI 1.4/2.0 RX Subsystem still has a built-in capability to optionally support both HDCP 1.4 and HDCP 2.3 decryption.

The following figure shows the internal structure of the HDMI 1.4/2.0 RX Subsystem when native video is selected as the video interface. In this illustration, both HDCP 1.4 and HDCP 2.3 are selected.

Figure 3. HDMI RX Subsystem Internal Structure in Native Video Interface Mode

The following figure shows the internal structure of the HDMI 1.4/2.0 RX Subsystem when Native Video (Vectored DE) interface is selected as the video interface. In this illustration, both HDCP 1.4 and HDCP 2.3 are selected.

Figure 4. HDMI 1.4/2.0 RX Subsystem Internal Structure in Native Video (Vectored DE) Interface Mode

The data width of the video interface is configured in the Vivado IDE by setting the Number of Pixels Per Clock on Video Interface and the Max Bits Per Component parameters.

The audio interface is a 32-bit AXI4-Stream master bus. The subsystem converts the captured audio to a multiple channel AXI audio stream and outputs the audio data on this interface.

The CPU interface is an AXI4-Lite bus interface, which is connected to a MicroBlaze™, Zynq-7000 SoC, Zynq® UltraScale+™ MPSoC, or Versal™ ACAP processor. Multiple sub-modules are used to construct the HDMI 1.4/2.0 RX Subsystem and all the sub-modules which require software access are connected through an AXI crossbar. Therefore, the MicroBlaze™, Zynq-7000 SoC, Zynq UltraScale+ MPSoC, or Versal ACAP processor is able to access and control each individual sub-modules inside the HDMI 1.4/2.0 RX Subsystem.

Important: The direct register level access to any of the sub-modules is not supported.

The HDMI 1.4/2.0 RX Subsystem device driver has an abstract layer of API to allow you to implement certain functions. This AXI4-Lite slave interface supports single beat read and write data transfers (no burst transfers).

The HDMI 1.4/2.0 RX Subsystem is connected to a Xilinx Video PHY Controller/HDMI GT Subsystem, which takes electronic signals from an HDMI cable and translates it into HDMI stream. Then, the HDMI 1.4/2.0 RX Subsystem converts the HDMI stream into video stream and audio stream. Based on the configuration selected, the HDMI 1.4/2.0 RX Subsystem sends the video stream in either Native Video format or AXI4-Stream format together with the AXI4-Stream Audio to other processing modules.

Note: The HDMI GT Subsystem comprises of the HDMI GT Controller IP and the Versal ACAPs Transceivers Wizard IP. For more information HDMI GT Controller LogiCORE IP Product Guide (PG334).

The subsystem also supports the features described in the following sections.