- Launch the Xilinx System Debugger by selecting .
- In the Xilinx command shell window, change to the
Example Design Project directory.
vivado% cd ./<IP instance name>_ex
- Invoke Xilinx System Debugger
(xsdb).
Vivado% xsdb
- Establish connections to debug targets.
xsdb% connect
- List all available JTAG
targets.
xsdb% targets 1 Versal vjtag40 2 RPU (PS POR is active) 3 Cortex-R5 #0 (PS POR is active) 4 Cortex-R5 #1 (PS POR is active) 5 APU (FPD domain isolation) 6 Cortex-A72 #0 (FPD domain isolation) 7 Cortex-A72 #1 (FPD domain isolation) 8 PPU 9 MicroBlaze PPU (Sleeping after reset) 10 PSM 11 PMC 12 PL
- Download the bitstream to the
FPGA.
xsdb% device program ./<IP instance name>_ex.runs/impl_1/exdes_wrapper.pdi xsdb% after 1000
- Set the target
processor.
xsdb% targets -set -filter {name =~ "Cortex-A72 #0"} xsdb% rst -proc xsdb% after 1000
- Download the software
.elf
to the FPGA.xsdb% dow ./<vitis_workspace>/<application_name>_1/Debug/<application_name>_1.elf
- Run the software.
xsdb% con
- Exit the XSDB command
prompt.
xsdb% exit