The subsystem supports the following two bits in the SCDC register address offset 0x20 for TMDS configurations (Table 10-19 of the HDMI 2.0 specification).
- Bit 1: TMDS_Bit_Clock_Ratio
- Bit 0: Scrambling_Enable
Two APIs are available in the driver to use this feature.
XV_HdmiRx_DdcScdcEnableis used to enable the SCDC register
XV_HdmiRx_DdcScdcClearis used to clear the SCDC register