256-bit AXI4-Stream Ports - 3.2 English

40G/50G High Speed Ethernet Subsystem Product Guide (PG211)

Document ID: PG211
Release Date: 2021-10-27
Version: 3.2 English

Ports under this section are available when Ethernet MAC + PCS/PMA with the 256-bit AXI4-Stream option is selected from the Configuration tab.

Table 1. 256-bit AXI4-Stream Ports
Name	Size	I/O	Description
tx_axis_tready_*	1	O	AXI4-Stream acknowledge signal to indicate to start the Data transfer.
tx_axis_tvalid_*	1	I	AXI4-Stream Data Valid Input
tx_axis_tdata_*	256	I	AXI4-Stream Data
tx_axis_tuser_*	1	I	AXI4-Stream User Sideband interface. 1 indicates a bad packet has been received. 0 indicates a good packet has been received.
tx_axis_tlast_*	1	I	AXI4-Stream signal indicating End of Ethernet Packet
tx_axis_tkeep_*	32	I	AXI4-Stream Data Control
rx_axis_tdata_*	256	O	AXI4-Stream Data to user logic.
rx_axis_tvalid_*	1	O	AXI4-Stream Data Valid. When this signal is 1, there is valid data on the RX AXI bus.
rx_axis_tuser_*	1	O	AXI4-Stream User Sideband interface. 1 indicates a bad packet has been received. 0 indicates a good packet has been received.
rx_axis_tlast_*	1	O	AXI4-Stream signal indicating an end of packet.
rx_axis_tkeep_*	32	O	AXI4-Stream Data Control to upper layer.