The following figure describes the port list for the AXI processor interface.
| Signal | I/O | Description |
|---|---|---|
| s_axi_aclk | I | AXI4-Lite clock. Range between 10 MHz and 300 MHz |
| s_axi_aresetn | I | Asynchronous active-Low reset |
| s_axi_awaddr[31:0] | I | Write address Bus |
| s_axi_awvalid | I | Write address valid |
| s_axi_awready | O | Write address acknowledge |
| s_axi_wdata[31:0] | I | Write data bus |
| s_axi_wstrb[3:0] | I | Strobe signal for the data bus byte lane |
| s_axi_wvalid | O | Write data valid |
| s_axi_wready | O | Write data acknowledge |
| s_axi_bresp[1:0] | O | Write transaction response |
| s_axi_bvalid | O | Write response valid |
| s_axi_bready | I | Write response acknowledge |
| s_axi_araddr[31:0] | I | Read address bus |
| s_axi_arvalid | I | Read address valid |
| s_axi_arready | O | Read address acknowledge |
| s_axi_rdata[31:0] | O | Read data output |
| s_axi_rresp[1:0] | O | Read data response |
| s_axi_rvalid | O | Read data/response valid |
| s_axi_rready | I | Read data acknowledge |
| pm_tick | I | Top level signal to read statistics counters; requires MODE_REG[30] (tick_reg_mode_sel) to be set to 0. |
Additional information for the operation of the AXI4 bus
is found in “Xilinx AXI Memory-Mapped Protocol Version 1.8”. As noted previously,
the top-level signal pm_tick can be used to read
statistics counters instead of the configuration register TICK_REG. In this case,
configuration register MODE_REG bit 30 (tick_reg_mode_sel) should be set to 0. If
tick_reg_mode_sel is set to 1, tick_reg is used to
read the statistics counters.