In the AXI4-Stream interface, the following tables describe the clock/reset signals, the Receive interface signals, and the Transmit interface signals.
Name | I/O | Clock Domain | Description |
---|---|---|---|
clk | I | AXI4-Stream clock. All signals between the 40G/50G High Speed Ethernet Subsystem and the user-side logic are synchronized to the positive edge of this signal. | |
dclk | I | This must be a convenient stable clock, for example 75 MHz. Refer to the current transceiver guide for up to date information. | |
rx_reset | I | Reset for the RX circuits. This signal is active-High (1 = reset) and must be held High until clk is stable. The 40G/50G High Speed Ethernet Subsystem handles synchronizing the rx_reset input to the appropriate clock domains within the core. This is a synchronous reset. | |
refclk_n0 | I | Differential reference clock for the transceiver (N). | |
refclk_p0 | I | Differential reference clock for the transceiver (P). | |
tx_reset | I | Reset for the TX circuits. This signal is active-High (1 = reset) and must be held High until clk is stable. The 40G/50G High Speed Ethernet Subsystem handles synchronizing the tx_reset input to the appropriate clock domains within the core. This is a synchronous reset. |