The clocking architecture for the Auto-Negotiation and Link Training blocks are illustrated in the following figure. Note that these blocks are not included unless the 50GBASE-KR or 50GBASE-CR feature is selected.
The Auto-Negotiation and Link Training blocks function independently from the MAC and PCS, and therefore they are on different clock domains.
tx_serdes_clk
The tx_serdes_clk drives the TX line side logic for
the Auto-Negotiation and Link Training. The DME frame is generated on this clock
domain.
rx_serdes_clk
The rx_serdes_clk drives the RX line side logic for
the Auto-Negotiation and Link Training.
AN_clk
The AN_clk drives the Auto-Negotiation state
machine. All ability signals are on this clock domain. The AN_clk can be any convenient frequency. In the example design, AN_clk is connected to the dclk input, which has a typical frequency of 75 MHz. The AN_clk frequency must be known to the Auto-Negotiation
state machine because it is the reference for all timers.