Continuous data transfer on the transmit AXI4-Stream interface is possible, as the signal tx_axis_tvalid can remain continuously High, with packet boundaries defined solely by tx_axis_tlast asserted for the end of the Ethernet packet. However, the core can deassert the tx_axis_tready acknowledgment signal to throttle the client data rate as required. See the following figure.
The client data logic can update the AXI4-Stream interface with valid data while the core has deasserted the tx_axis_tready acknowledgment signal. However, when valid is asserted and new data has been placed on the AXI4-Stream, it should remain there until the core has asserted tx_axis_tready.
Figure 1. Back to Back Continuous Transfer – 256-bit AXI4-Stream
