Changes from v2.2 to v2.3 - 3.2 English

Port Changes

• Corrected port name from rx_serdes_resetn to rx_serdes_reset in figure in Port Descriptions.
• Added text about 2-step 1588 operation to tx_ptp_tstamp_out[80-1:0] and tx_ptp_tstamp_out_* descriptions.
• ctl_tx_ptp_latency_adjust[10:0] signal

  Deleted sentence about 802 decimal clock mode value.

• Updated axi_ctl_core_mode_switch to update 0x018C to 0x013C.
• Changed name from restart_tx_rx_0 to restart_tx_rx_*

Ports Added

• tx_ptp_upd_chksum_in
• tx_ptp_pcslane_out
• tx_ptp_chksum_offset_in
• rx_ptp_pcslane_out
• rx_lane_aligner_fill
• rx_ptp_tstamp_valid_out

• send_continuous_pkts_*
• restart_tx_rx_0
• mode_change_0
• core_speed_0

Ports Removed

• tx_ptp_rxtstamp_in
• tx_ptp_rxtstamp_in

Registers Added

• STAT_CORE_SPEED_REG: 047C
• user_reg0_*
• RXOUTCLKSEL_IN_*
• TXOUTCLKSEL_IN_*

Register Name Changed

• Updated SWITCH_CORE_SPEED_REG: 0180 to SWITCH_CORE_SPEED_REG: 013C.
• Changed USER_REG_0: 0184 to USER_REG_0: 0138.

Registers Deleted

• USER_REG_1: 0188
• CORE_SPEED_REG:180