Common Transceiver Ports for UltraScale/UltraScale+ Devices - 3.2 English

40G/50G High Speed Ethernet Subsystem Product Guide (PG211)
Document ID
PG211
Release Date
2021-10-27
Version
3.2 English
Table 1. Common Transceiver Ports for UltraScale/UltraScale+ Devices
Name Size I/O Description
gt_loopback_in 6/12 I GT loopback input signal. Refer to the GT user guide.

6-bit width for the 50G single core, 12-bit width for 40G single core/ 50G two core and Include GT subcore in core option selected from the GT Selection and Configuration tab).
gt_rxp_in_0 1 I Differential serial GT RX input for lane 0.

This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab.
gt_rxn_in_0 1 I Differential serial GT RX input for lane 0.

This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab.
gt_rxp_in_1 1 I Differential serial GT RX input for lane 1.

This port is available when Include GT subcore in core option selected in the GT Selection and Configuration tab.
gt_rxn_in_1 1 I Differential serial GT RX input for lane 1.

This port is available when Include GT subcore in core option selected in the GT Selection and Configuration tab.
gt_rxp_in_2 1 I Differential serial GT RX input for lane 2.

This port is available for 40G and 50G two core and the Include GT subcore in core option is selected from the GT Selection and Configuration tab.
gt_rxn_in_2 1 I Differential serial GT RX input for lane 2.

This port is available for 40G and 50G two cores and the Include GT subcore in core option selected from the GT Selection and Configuration tab.
gt_rxp_in_3 1 I Differential serial GT RX input for lane 3.

This port is available for 40G and 50G two cores and the Include GT subcore in core option is selected from the GT Selection and Configuration tab.
gt_rxn_in_3 1 I Differential serial GT RX input for lane 3.

This port is available for 40G and 50G two cores and the Include GT subcore in core option is selected from the GT Selection and Configuration tab.
gt_txp_out_0 1 O Differential serial GT TX output for lane 0.

This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab.
gt_txn_out_0 1 O Differential serial GT TX output for lane 0.

This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab.
gt_txp_out_1 1 O Differential serial GT TX output for lane 1.

This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab.
gt_txn_out_1 1 O Differential serial GT TX output for lane 1.

This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab.
gt_txp_out_2 1 O Differential serial GT TX output for lane 2.

This port is available for 40G and 50G two cores and the Include GT subcore in core option is selected from the GT Selection and Configuration tab.
gt_txn_out_2 1 O Differential serial GT TX output for lane 2.

This port is available for 40G and 50G two cores and the Include GT subcore in core option is selected from the GT Selection and Configuration tab.
gt_txp_out_3 1 O Differential serial GT TX output for lane 3.

This port is available for 40G and 50G two cores and the Include GT subcore in core option is selected from the GT Selection and Configuration tab.
gt_txn_out_3 1 O Differential serial GT TX output for lane 3.

This port is available for 40G and 50G two cores and the Include GT subcore in core option is selected from the GT Selection and Configuration tab.
gt_txp_out 1/2 O

Differential serial GT TX output

This port is available for Board Support.
gt_txn_out 1/2 O

Differential serial GT TX output

This port is available for Board Support.
gt_txp_in 1/2 O

Differential serial GT TX input

This port is available for Board Support.
gt_txn_in 1/2 I

Differential serial GT TX input

This port is available for Board Support.
gt_loopback_out_* 1 O GT loopback output signal from AXI4-Lite register map. See the appropriate GT user guide.

This port is available when the Include GT subcore in example design option is selected in the GT Selection and Configuration tab and the AXI4-Lite interface is selected from configuration tab.
rxgearboxslip_out_* 1 O Rxgearboxslip signal from core to GT.

This port is available when the Include GT subcore in example design option is selected in the GT Selection and Configuration tab.
rxdatavalid_in_* 2/4 I RX data valid signal from GT to core.

This port is available when the Include GT subcore in example design option is selected in the GT Selection and Configuration tab.
rxheader_in_* 6/12 I RX header signal from GT to core.

This port is available when the Include GT subcore in example design option is selected in the GT Selection and Configuration tab.
rxheadervalid_in_* 2/4 I RX header valid signal from GT to core.

This port is available when the Include GT subcore in example design option is selected in the GT Selection and Configuration tab.
rx_serdes_data_in_* 255 I TX data signal from core to GT.

This port is available when the Include GT subcore in example design option is selected in the GT Selection and Configuration tab.
txheader_out_* 6/12 O TX header signal from core to GT.

This port is available when the Include GT subcore in example design option is selected in the GT Selection and Configuration tab.
tx_serdes_data_out_* 255 O TX data signal from core to GT.

This port is available when the Include GT subcore in example design option is selected in the GT Selection and Configuration tab.
txsequence_out_* 7 O TX sequence signal from the core to the GT.