Several issues can commonly occur during the first hardware test of an Ethernet IP core. These should be checked as indicated in the following subsections.
It is assumed that the Ethernet IP core has already passed all simulation testing which is being implemented in hardware. This is a prerequisite for any kind of hardware debug.
The usual sequence of debugging is to proceed in the following sequence:
- Clean up signal integrity.
- Ensure that each SerDes achieves clock data recovery (CDR) lock.
- Check that each lane has achieved word alignment.
- Check that lane alignment has been achieved.
- Proceed to Interface and Protocol debug.