The previous figure shows the instantiation of various modules and their
hierarchy for a single core configuration of the l_ethernet_0 example design when the GT (serial transceiver) is outside
the IP core, that is, in the example design. This hierarchical example design is
delivered when you select the Include GT subcore in
the example design option from the GT Selection and
Configuration tab.
The l_ethernet_0_core_support.v is present in the hierarchy when you select the Include GT subcore in example design option from the GT Selection and Configuration tab or the Include Shared Logic in example design option from the Shared Logic tab. This instantiates the l_ethernet_0_sharedlogic_wrapper.v module and the l_ethernet_0.v module for the Include Shared Logic in example design option. The l_ethernet_0_gt_wrapper.v module will be present when you select the GT subcore in example design option.
The l_ethernet_0.v module instantiates the necessary the sync registers/retiming pipeline registers for the synchronization of data between the core and the GT.
The l_ethernet_0_pkt_gen_mon module is used to generate the
data packets for sanity testing. The packet generation and checking is controlled by a
Finite State Machine (FSM) module.
The optional modules are described as follows:
- l_ethernet _0_sharedlogic_wrapper
- This module is present in the example design when you select the Include GT subcore in example design option from the GT Selection and Configuration tab or Include Shared Logic in the Example Design from the Shared Logic tab. This module brings all modules that can be shared between multiple IP cores and designs outside the IP core.
- l_ethernet _0_gt_wrapper
- This module is present in the example design when you select the Include GT subcore in example design option from the GT Selection and Configuration tab. This module instantiates the GT along with various helper blocks. The clocking helper blocks are used to generate the required clock frequency for the Core.
The following figure shows the instantiation of various modules and their
hierarchy for the multiple core configuration of the l_ethernet_0
example design when the GT is in the example design.
For the
Versal®
platform, the gt_quad_base (GT wizard for Versal) will be a part of the example design only; the 40G/50G High Speed Ethernet IP and GT (serial transceiver) IP will be
connected in the block design using the IP integrator (block automation).
The following figure is a block design, where the 40/50G Ethernet example design connected in the IP integrator. See the Vivado Design Suite Tutorial: Designing IP Subsystems Using IP Integrator (UG995) for more information on IP integrator.
When the 40G/50G High Speed Ethernet subsystem is added
to
Vivado®
IP integrator and Block Automation is
run the IP/core and GT (serial transceivers) will get connected with some helper blocks
as per the core configuration. There is a reset interface IP, internal to the 40G/50G High Speed Ethernet IP, used to release tx/rx mstreset to the Versal GT and
check for tx/rx mstresetdone status and reset
sequencing to the GT.
