IEEE PTP 1588v2 for 40G/50G Subsystem - 3.2 English

40G/50G High Speed Ethernet Subsystem Product Guide (PG211)

Document ID: PG211
Release Date: 2021-10-27
Version: 3.2 English

Introduction
Features
IP Facts
Overview
Navigating Content by Design Process
Subsystem Overview
Feature Summary
Applications
Licensing and Ordering
License Checkers
Product Specification
Typical Operation
Statistics Gathering
Testability Functions
Standards
Performance and Resource Utilization
Latency
Port Descriptions
Transceiver Ports
AXI4-Stream Interface
AXI4-Stream Interface – 128-bit Straddle Packet Interface
Receive AXI4-Stream Interface
Normal Frame Reception
Transmit AXI4-Stream Interface
AXI4-Stream Interface – 256-bit Packet Interface
AXI4-Stream Clocks and Reset
Transmit AXI4-Stream Interface - 256-bit
Data Lane Mapping - TX
Normal Transmission
Back to Back Continuous Transfer
Aborting a Transmission
Receive AXI4-Stream Interface – 256-bit
Data Lane Mapping - RX
Normal Frame Reception
Frame Reception with Errors
TX Path Control/Status Ports
RX Path Control/Status Ports
Miscellaneous Status/Control Ports
Statistics Interface Ports
Pause Interface Ports
Pause Interface - Control Ports
Pause Interface - RX Path Ports
Pause Interface - TX Path Ports
Auto-Negotiation (AN) and Link Training (LT)
Port List — Auto-Negotiation
Port List — Link Training
Overview
Auto-Negotiation Description
Link Training Description
Overview
Transmit
Receive
Board Testing of the 40G/50G High Speed Ethernet Using the AXI4-Lite Interface
Forward Error Correction (FEC)
PCS Variant
Features
Block Diagram
Port List — PCS-Only
Testability
PCS Clocking
XLGMII/50GMII Clocks
SerDes Clocks
AXI4-Lite Register Space
AXI4-Lite Ports
Base Pages
Configuration Registers
Status Registers
Statistics Counters
Register Definitions
Configuration Registers
GT_RESET_REG: 0000
RESET_REG: 0004
MODE_REG: 0008
CONFIGURATION_TX_REG1: 000C
CONFIGURATION_RX_REG1: 0014
CONFIGURATION_RX_MTU: 0018
CONFIGURATION_VL_LENGTH_REG: 001C
TICK_REG: 0020
CONFIGURATION_REVISION_REG: 0024
CONFIGURATION_1588_REG: 0038
CONFIGURATION_TX_FLOW_CONTROL_REG1: 0040
CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG1: 0044
CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG2: 0048
CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG3: 004C
CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG4: 0050
CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG5: 0054
CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG1: 0058
CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG2: 005C
CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG3: 0060
CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG4: 0064
CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG5: 0068
CONFIGURATION_TX_FLOW_CONTROL_PPP_ETYPE_OP_REG: 006C
CONFIGURATION_TX_FLOW_CONTROL_GPP_ETYPE_OP_REG: 0070
CONFIGURATION_TX_FLOW_CONTROL_GPP_DA_REG_LSB: 0074
CONFIGURATION_TX_FLOW_CONTROL_GPP_DA_REG_MSB: 0078
CONFIGURATION_TX_FLOW_CONTROL_GPP_SA_REG_LSB: 007C
CONFIGURATION_TX_FLOW_CONTROL_GPP_SA_REG_MSB: 0080
CONFIGURATION_TX_FLOW_CONTROL_PPP_DA_REG_LSB: 0084
CONFIGURATION_TX_FLOW_CONTROL_PPP_DA_REG_MSB: 0088
CONFIGURATION_TX_FLOW_CONTROL_PPP_SA_REG_LSB: 008C
CONFIGURATION_TX_FLOW_CONTROL_PPP_SA_REG_MSB: 0090
CONFIGURATION_RX_FLOW_CONTROL_REG1: 0094
CONFIGURATION_RX_FLOW_CONTROL_REG2: 0098
CONFIGURATION_RX_FLOW_CONTROL_PPP_ETYPE_OP_REG: 009C
CONFIGURATION_RX_FLOW_CONTROL_GPP_ETYPE_OP_REG: 00A0
CONFIGURATION_RX_FLOW_CONTROL_GCP_PCP_TYPE_REG: 00A4
CONFIGURATION_RX_FLOW_CONTROL_PCP_OP_REG: 00A8
CONFIGURATION_RX_FLOW_CONTROL_GCP_OP_REG: 00AC
CONFIGURATION_RX_FLOW_CONTROL_DA_REG1_LSB: 00B0
CONFIGURATION_RX_FLOW_CONTROL_DA_REG1_MSB: 00B4
CONFIGURATION_RX_FLOW_CONTROL_DA_REG2_LSB: 00B8
CONFIGURATION_RX_FLOW_CONTROL_DA_REG2_MSB: 00BC
CONFIGURATION_RX_FLOW_CONTROL_SA_REG1_LSB: 00C0
CONFIGURATION_RX_FLOW_CONTROL_SA_REG1_MSB: 00C4
CONFIGURATION_RSFEC_REG: 00D0
CONFIGURATION_FEC_REG: 00D4
CONFIGURATION_AN_CONTROL_REG1: 00E0
CONFIGURATION_AN_CONTROL_REG2: 00E4
CONFIGURATION_AN_ABILITY: 00F8
CONFIGURATION_LT_CONTROL_REG1: 0100
CONFIGURATION_LT_TRAINED_REG: 0104
CONFIGURATION_LT_PRESET_REG: 0108
CONFIGURATION_LT_INIT_REG: 010C
CONFIGURATION_LT_SEED_REG0: 0110
CONFIGURATION_LT_SEED_REG1: 0114
CONFIGURATION_LT_COEFFICIENT_REG0: 0130
CONFIGURATION_LT_COEFFICIENT_REG1: 0134
USER_REG_0: 0138
SWITCH_CORE_SPEED_REG: 013C
GT_WIZ_CHANNEL_LOOPBACK_REG: 0154
Status Registers
STAT_TX_STATUS_REG1: 0400
STAT_RX_STATUS_REG1: 0404
STAT_STATUS_REG1: 0408
STAT_RX_BLOCK_LOCK_REG: 040C
STAT_RX_LANE_SYNC_REG: 0410
STAT_RX_LANE_SYNC_ERR_REG: 0414
STAT_RX_AM_ERR_REG: 0418
STAT_RX_AM_LEN_ERR_REG: 041C
STAT_RX_AM_REPEAT_ERR_REG: 0420
STAT_RX_LANE_DEMUXED: 0424
STAT_RX_PCS_LANE_NUM_REG1: 0428
STAT_RX_RSFEC_STATUS_REG: 043C
STAT_RX_RSFEC_LANE_FILL_REG1: 0440
STAT_RX_FEC_STATUS_REG: 0448
STAT_TX_RSFEC_STATUS_REG: 044C
STAT_TX_FLOW_CONTROL_REG1: 0450
STAT_RX_FLOW_CONTROL_REG1: 0454
STAT_AN_STATUS: 0458
STAT_AN_ABILITY: 045C
STAT_AN_LINK_CTL: 0460
STAT_LT_STATUS_REG1: 0464
STAT_LT_STATUS_REG2: 0468
STAT_LT_STATUS_REG3: 046C
STAT_LT_STATUS_REG4: 0470
STAT_LT_COEFFICIENT0_REG: 0474
STAT_LT_COEFFICIENT1_REG: 0478
STAT_CORE_SPEED_REG: 047C
STAT_GT_WIZ_REG: 04A0
STAT_AN_LINK_CTL2: 09F0
Statistics Counters
STATUS_CYCLE_COUNT_LSB: 0500
STATUS_CYCLE_COUNT_MSB: 0504
STAT_RX_BIP_ERR_0_LSB: 0508
STAT_RX_BIP_ERR_0_MSB: 050C
STAT_RX_BIP_ERR_1_LSB: 0510
STAT_RX_BIP_ERR_1_MSB: 0514
STAT_RX_BIP_ERR_2_LSB: 0518
STAT_RX_BIP_ERR_2_MSB: 051C
STAT_RX_BIP_ERR_3_LSB: 0520
STAT_RX_BIP_ERR_3_MSB: 0524
STAT_RX_FRAMING_ERR_0_LSB: 05A8
STAT_RX_FRAMING_ERR_0_MSB: 05AC
STAT_RX_FRAMING_ERR_1_LSB: 05B0
STAT_RX_FRAMING_ERR_1_MSB: 05B4
STAT_RX_FRAMING_ERR_2_LSB: 05B8
STAT_RX_FRAMING_ERR_2_MSB: 05BC
STAT_RX_FRAMING_ERR_3_LSB: 05C0
STAT_RX_FRAMING_ERR_3_MSB: 05C4
STAT_RX_BAD_CODE_LSB: 0660
STAT_RX_BAD_CODE_MSB: 0664
STAT_RX_ERROR_LSB: 0668
STAT_RX_ERROR_MSB: 066C
STAT_RX_RSFEC_CORRECTED_CW_INC_LSB: 0670
STAT_RX_RSFEC_CORRECTED_CW_INC_MSB: 0674
STAT_RX_RSFEC_UNCORRECTED_CW_INC_LSB: 0678
STAT_RX_RSFEC_UNCORRECTED_CW_INC_MSB: 067C
STAT_RX_RSFEC_ERR_COUNT0_INC_LSB: 0680
STAT_RX_RSFEC_ERR_COUNT0_INC_MSB: 0684
STAT_RX_RSFEC_ERR_COUNT1_INC_LSB: 0688
STAT_RX_RSFEC_ERR_COUNT1_INC_LSB: 068C
STAT_TX_FRAME_ERROR_LSB: 06A0
STAT_TX_FRAME_ERROR_MSB: 06A4
STAT_TX_TOTAL_PACKETS_LSB: 0700
STAT_TX_TOTAL_PACKETS_MSB: 0704
STAT_TX_TOTAL_GOOD_PACKETS_LSB: 0708
STAT_TX_TOTAL_GOOD_PACKETS_MSB: 070C
STAT_TX_TOTAL_BYTES_LSB: 0710
STAT_TX_TOTAL_BYTES_MSB: 0714
STAT_TX_TOTAL_GOOD_BYTES_LSB: 0718
STAT_TX_TOTAL_GOOD_BYTES_MSB: 071C
STAT_TX_PACKET_64_BYTES_LSB: 0720
STAT_TX_PACKET_64_BYTES_MSB: 0724
STAT_TX_PACKET_65_127_BYTES_LSB: 0728
STAT_TX_PACKET_65_127_BYTES_MSB: 072C
STAT_TX_PACKET_128_255_BYTES_LSB: 0730
STAT_TX_PACKET_128_255_BYTES_MSB: 0734
STAT_TX_PACKET_256_511_BYTES_LSB: 0738
STAT_TX_PACKET_256_511_BYTES_MSB: 073C
STAT_TX_PACKET_512_1023_BYTES_LSB: 0740
STAT_TX_PACKET_512_1023_BYTES_MSB: 0744
STAT_TX_PACKET_1024_1518_BYTES_LSB: 0748
STAT_TX_PACKET_1024_1518_BYTES_MSB: 074C
STAT_TX_PACKET_1519_1522_BYTES_LSB: 0750
STAT_TX_PACKET_1519_1522_BYTES_MSB: 0754
STAT_TX_PACKET_1523_1548_BYTES_LSB: 0758
STAT_TX_PACKET_1523_1548_BYTES_MSB: 075C
STAT_TX_PACKET_1549_2047_BYTES_LSB: 0760
STAT_TX_PACKET_1549_2047_BYTES_MSB: 0764
STAT_TX_PACKET_2048_4095_BYTES_LSB: 0768
STAT_TX_PACKET_2048_4095_BYTES_MSB: 076C
STAT_TX_PACKET_4096_8191_BYTES_LSB: 0770
STAT_TX_PACKET_4096_8191_BYTES_MSB: 0774
STAT_TX_PACKET_8192_9215_BYTES_LSB: 0778
STAT_TX_PACKET_8192_9215_BYTES_MSB: 077C
STAT_TX_PACKET_LARGE_LSB: 0780
STAT_TX_PACKET_LARGE_MSB: 0784
STAT_TX_PACKET_SMALL_LSB: 0788
STAT_TX_PACKET_SMALL_MSB: 078C
STAT_TX_BAD_FCS_LSB: 07B8
STAT_TX_BAD_FCS_MSB: 07BC
STAT_TX_UNICAST_LSB: 07D0
STAT_TX_UNICAST_MSB: 07D4
STAT_TX_MULTICAST_LSB: 07D8
STAT_TX_MULTICAST_MSB: 07DC
STAT_TX_BROADCAST_LSB: 07E0
STAT_TX_BROADCAST_MSB: 07E4
STAT_TX_VLAN_LSB: 07E8
STAT_TX_VLAN_MSB: 07EC
STAT_TX_PAUSE_LSB: 07F0
STAT_TX_PAUSE_MSB: 07F4
STAT_TX_USER_PAUSE_LSB: 07F8
STAT_TX_USER_PAUSE_MSB: 07FC
STAT_RX_TOTAL_PACKETS_LSB: 0808
STAT_RX_TOTAL_PACKETS_MSB: 080C
STAT_RX_TOTAL_GOOD_PACKETS_LSB: 0810
STAT_RX_TOTAL_GOOD_PACKETS_MSB: 0814
STAT_RX_TOTAL_BYTES_LSB: 0818
STAT_RX_TOTAL_BYTES_MSB: 081C
STAT_RX_TOTAL_GOOD_BYTES_LSB: 0820
STAT_RX_TOTAL_GOOD_BYTES_MSB: 0824
STAT_RX_PACKET_64_BYTES_LSB: 0828
STAT_RX_PACKET_64_BYTES_MSB: 082C
STAT_RX_PACKET_65_127_BYTES_LSB: 0830
STAT_RX_PACKET_65_127_BYTES_MSB: 0834
STAT_RX_PACKET_128_255_BYTES_LSB: 0838
STAT_RX_PACKET_128_255_BYTES_MSB: 083C
STAT_RX_PACKET_256_511_BYTES_LSB: 0840
STAT_RX_PACKET_256_511_BYTES_MSB: 0844
STAT_RX_PACKET_512_1023_BYTES_LSB: 0848
STAT_RX_PACKET_512_1023_BYTES_MSB: 084C
STAT_RX_PACKET_1024_1518_BYTES_LSB: 0850
STAT_RX_PACKET_1024_1518_BYTES_MSB: 0854
STAT_RX_PACKET_1519_1522_BYTES_LSB: 0858
STAT_RX_PACKET_1519_1522_BYTES_MSB: 085C
STAT_RX_PACKET_1523_1548_BYTES_LSB: 0860
STAT_RX_PACKET_1523_1548_BYTES_MSB: 0864
STAT_RX_PACKET_1549_2047_BYTES_LSB: 0868
STAT_RX_PACKET_1549_2047_BYTES_MSB: 086C
STAT_RX_PACKET_2048_4095_BYTES_LSB: 0870
STAT_RX_PACKET_2048_4095_BYTES_MSB: 0874
STAT_RX_PACKET_4096_8191_BYTES_LSB: 0878
STAT_RX_PACKET_4096_8191_BYTES_MSB: 087C
STAT_RX_PACKET_8192_9215_BYTES_LSB: 0880
STAT_RX_PACKET_8192_9215_BYTES_MSB: 0884
STAT_RX_PACKET_LARGE_LSB: 0888
STAT_RX_PACKET_LARGE_MSB: 088C
STAT_RX_PACKET_SMALL_LSB: 0890
STAT_RX_PACKET_SMALL_MSB: 0894
STAT_RX_UNDERSIZE_LSB: 0898
STAT_RX_UNDERSIZE_MSB: 089C
STAT_RX_FRAGMENT_LSB: 08A0
STAT_RX_FRAGMENT_MSB: 08A4
STAT_RX_OVERSIZE_LSB: 08A8
STAT_RX_OVERSIZE_MSB: 08AC
STAT_RX_TOOLONG_LSB: 08B0
STAT_RX_TOOLONG_MSB: 08B4
STAT_RX_JABBER_LSB: 08B8
STAT_RX_JABBER_MSB: 08BC
STAT_RX_BAD_FCS_LSB: 08C0
STAT_RX_BAD_FCS_MSB: 08C4
STAT_RX_PACKET_BAD_FCS_LSB: 08C8
STAT_RX_PACKET_BAD_FCS_MSB: 08CC
STAT_RX_STOMPED_FCS_LSB: 08D0
STAT_RX_STOMPED_FCS_MSB: 08D4
STAT_RX_UNICAST_LSB: 08D8
STAT_RX_UNICAST_MSB: 08DC
STAT_RX_MULTICAST_LSB: 08E0
STAT_RX_MULTICAST_MSB: 08E4
STAT_RX_BROADCAST_LSB: 08E8
STAT_RX_BROADCAST_MSB: 08EC
STAT_RX_VLAN_LSB: 08F0
STAT_RX_VLAN_MSB: 08F4
STAT_RX_PAUSE_LSB: 08F8
STAT_RX_PAUSE_MSB: 08FC
STAT_RX_USER_PAUSE_LSB: 0900
STAT_RX_USER_PAUSE_MSB: 0904
STAT_RX_INRANGEERR_LSB: 0908
STAT_RX_INRANGEERR_MSB: 090C
STAT_RX_TRUNCATED_LSB: 0910
STAT_RX_TRUNCATED_MSB: 0914
STAT_RX_TEST_PATTERN_MISMATCH_LSB: 0918
STAT_RX_TEST_PATTERN_MISMATCH_MSB: 091C
STAT_FEC_INC_CORRECT_COUNT_LSB: 0920
STAT_FEC_INC_CORRECT_COUNT_MSB: 0924
STAT_FEC_INC_CANT_CORRECT_COUNT_LSB: 0928
STAT_FEC_INC_CANT_CORRECT_COUNT_MSB: 092C
Designing with the Subsystem
General Design Guidelines
Use the Example Design
Know the Degree of Difficulty
Registering Signals
Recognize Timing Critical Signals
Make Only Allowed Modifications
Clocking
PCS/PMA Only Clocking
40G/50G MAC with PCS/PMA Clocking
Low Latency 40G/50G MAC with PCS/PMA Clocking
Auto-Negotiation and Link Training Clocking
LogiCORE Example Design Clocking and Resets
Single Core (1x50G) - Asynchronous Clock Mode (GTY) (2x25G) for UltraScale/UltraScale+ Device
Single Core (1x50G) - Asynchronous Clock Mode (GTY) (2x25G) for Versal ACAP
Multiple Cores (2x50G) - Asynchronous Clock Mode GTY (2x25G) for UltraScale/UltraScale+ Device
Single Core (1x50G) - Asynchronous Clock Mode GTM UltraScale+ (1x50G)
Multiple Cores (2x50G) - Asynchronous Clock Mode GTM UltraScale+ (2x50G)
Single Core (1x40G) - Asynchronous Clock Mode GTY/GTH (4x10G)
SerDes Data Mapping for GTM
IEEE PTP 1588v2 for 40G/50G Subsystem
Overview
Egress
Ingress
1588v2 Port List and Descriptions
IEEE PTP 1588v2 Functional Description
Performance
RS-FEC Support
RS-FEC Functional Description
RS-FEC Configuration and Status Port List and Descriptions
Status/Control Interface
RX and TX PCS Lane Marker Values
RX PCS Lane Alignment Status
RX Error Status
Design Flow Steps
Customizing and Generating the Subsystem
Xilinx IP - GT Quad Integration for Versal ACAP
Configuration Tab
MAC Options Tab
GT Selection and Configuration Tab
Shared Logic Tab
Configuration Spreadsheet
Output Generation
Constraining the Subsystem
Simulation
Synthesis and Implementation
Example Design
Example Design Hierarchy
Example Design Hierarchy (GT in Example Design)
User Interface
Core xci Top Level Port List
Common Clock/Reset Signals
Common Transceiver Ports for UltraScale/UltraScale+ Devices
Common Transceiver Ports for Versal ACAP
Transceiver Control and Status Debug Ports
AXI4-Lite Interface Ports
128-bit Straddled AXI4-Stream User Interface Signals
256-bit AXI4-Stream Ports
MII User Interface Signals
TX Path Control/Status/Statistics Signals
RX Path Control/Status/Statistics Signals
TX Pause Interface Control/Status/Statistics Signals
RX Pause Interface Control/Status/Statistics Signals
IEEE 1588 TX/RX Interface Control/Status/Statistics Signals
AN and LT Interface Control/Status/Statistics Signals
Clause 74 FEC Interface Control/Status/Statistics Signals
Clause 91 RS-FEC Interface Control/Status/Statistics Signals
Runtime Switch Signals
Duplex Mode of Operation
Run Time Switchable
Shared Logic Implementation
AXI4-Lite Interface Implementation
.h Header File
AXI4-Lite Interface User Logic
User State Machine
AXI4-Lite User Interface Ports
User Side AXI4-Lite Write / Read Transactions
IEEE Clause 91 (RS-FEC) Integration
Test Bench
Upgrading
Changes from v2.2 to v2.3
Changes from v2.1 to v2.2
Changes from v2.0 to v2.1
Changes from v2.0 (10/05/2016) to v2.0 (11/30/2016 version)
Changes from v1.1 to v2.0
Changes from v1.0 to v1.1
Debugging
Finding Help on Xilinx.com
Documentation
Answer Records
Master Answer Record for the 40G/50G High Speed Ethernet Subsystem
Technical Support
Debug Tools
Example Design
Vivado Design Suite Debug Feature
Reference Boards
Simulation Debug
Simulator License Availability
Library File Location
Version Compatibility
Slow Simulation
Simulation Fails Before Completion
Simulation Completes But Fails
Hardware Debug
General Checks
Transceiver Specific Checks
Ethernet Specific Checks
Signal Integrity
Lane Swapping
N/P Swapping
Clocking and Resets
Interface Debug
AXI4-Stream Interfaces
TX Debug (Buffer Errors)
RX Debug (Buffer Errors)
Protocol Debug
Alignment Marker Spacing
Diagnostic Signals
Statistics Counters
Debugging Auto-Negotiation and Link Training
Debugging Auto-Negotiation and Link Training Using AXI4-Lite Interface
Pause Processing Interface
TX Pause Generation
RX Pause Termination
Determining Pause Packets
User Interface
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

Back to home page