The 40G/50G High Speed Ethernet Subsystem has separate reset inputs for the RX and TX paths that can be asserted independently. Within the RX and TX paths, there are resets for each of the various clock domains. The reset procedure is simple and the only requirement is that a reset must be asserted when the corresponding clock is not stable.
The 40G/50G High Speed Ethernet Subsystem takes care of ensuring that the different resets properly interact with each other internally and the interface operates properly (that is, there is no order required for asserting/deasserting different resets). It is left up to you to ensure a reset is held until the corresponding clock is fully stable.
The following figures illustrate the clocking and reset structure when you implement the Example Design using the Vivado tools.