MODE_REG: 0008 - 3.2 English

40G/50G High Speed Ethernet Subsystem Product Guide (PG211)
Document ID
PG211
Release Date
2021-10-27
Version
3.2 English
Table 1. MODE_REG: 0008
Bits Default Type Signal
0 1 RW en_wr_slverr_indication
1 1 RW en_rd_slverr_indication
30 1 RW tick_reg_mode_sel
31 0 RW GT near-end PMA loopback
  1. The 0th and 1st bit of mode_reg register provides the flexibility to disable or enable the slv error. The user can write '0' to these bits to suppress the reporting of slv error.