The following table describes the other status/control signals.
| Name | I/O | Clock Domain | Description |
|---|---|---|---|
| ctl_tx_ipg_value[3:0] | I |
This signal can be optionally present. The ctl_tx_ipg_value defines the target average minimum Inter Packet Gap (IPG, in bytes) inserted between rx_serdes_clk packets. Typical value is 12. The ctl_tx_ipg_value can also be programmed to a value in the 0 to 7 range, but in that case, it is interpreted as meaning "minimal IPG", so only Terminate code word IPG is inserted; no Idles are ever added in that case and that produces an average IPG of around 4 bytes when random-size packets are transmitted. |
|
| stat_rx_got_signal_os | O | rx_clk_out | Signal OS indication. If this bit is sampled as a
1, it indicates that a Signal OS word was received. Note: Signal OS should not be received in
an Ethernet network
|
| ctl_rx_process_lfi | I | rx_clk_out | When this input is set to 1, the RX core expects and processes Local Fault (LF) control codes coming in from the SerDes. When set to 0, the RX core ignores LF control codes coming in from the SerDes. |
| ctl_rx_test_pattern | I | rx_clk_out | Test pattern checking enable for the RX core. A value of 1 enables test mode as defined in Clause 82.2.17. Corresponds to MDIO register bit 3.42.2 as defined in Clause 82.3. Checks for scrambled idle pattern. |
| ctl_tx_test_pattern | I | clk | Test pattern generation enable for the TX core. A value of 1 enables test mode as defined in Clause 82.2.10. Corresponds to MDIO register bit 3.42.7 as defined in Clause 82.3. Generates a scrambled idle pattern. |
| stat_rx_test_pattern_mismatch[3|2|1|0:0] | O | rx_clk_out | Test pattern mismatch increment. A non zero value in any cycle indicates how many mismatches occurred for the test pattern in the RX core. This output is only active when ctl_rx_test_pattern is set to a 1. This output can be used to generate MDIO register 3.43.15:0 as defined in Clause 82.3. This output is pulsed for one clock cycle. |