The following table describes the RX path ports.
| Name | I/O | Clock Domain | Description |
|---|---|---|---|
| ctl_rx_enable_gcp | I | rx_serdes_clk | A value of 1 enables global control packet processing. |
| ctl_rx_check_mcast_gcp | I | rx_serdes_clk | A value of 1 enables global control multicast destination address processing. |
| ctl_rx_check_ucast_gcp | I | rx_serdes_clk | A value of 1 enables global control unicast destination address processing. |
| ctl_rx_pause_da_ucast[47:0] | I | rx_serdes_clk | Unicast destination address for pause processing. |
| ctl_rx_check_sa_gcp | I | rx_serdes_clk | A value of 1 enables global control source address processing. |
| ctl_rx_pause_sa[47:0] | I | rx_serdes_clk | Source address for pause processing. |
| ctl_rx_check_etype_gcp | I | rx_serdes_clk | A value of 1 enables global control ethertype processing. |
| ctl_rx_check_opcode_gcp | I | rx_serdes_clk | A value of 1 enables global control opcode processing. |
| ctl_rx_opcode_min_gcp[15:0] | I | rx_serdes_clk | Minimum global control opcode value. |
| ctl_rx_opcode_max_gcp[15:0] | I | rx_serdes_clk | Maximum global control opcode value. |
| ctl_rx_etype_gcp[15:0] | I | rx_serdes_clk | Ethertype field for global control processing. |
| ctl_rx_enable_pcp | I | rx_serdes_clk | A value of 1 enables priority control packet processing. |
| ctl_rx_check_mcast_pcp | I | rx_serdes_clk | A value of 1 enables priority control multicast destination address processing. |
| ctl_rx_check_ucast_pcp | I | rx_serdes_clk | A value of 1 enables priority control unicast destination address processing. |
| ctl_rx_pause_da_mcast[47:0] | I | rx_serdes_clk | Multicast destination address for pause processing. |
| ctl_rx_check_sa_pcp | I | rx_serdes_clk | A value of 1 enables priority control source address processing. |
| ctl_rx_check_etype_pcp | I | rx_serdes_clk | A value of 1 enables priority control ethertype processing. |
| ctl_rx_etype_pcp[15:0] | I | rx_serdes_clk | Ethertype field for priority control processing. |
| ctl_rx_check_opcode_pcp | I | rx_serdes_clk | A value of 1 enables priority control opcode processing. |
| ctl_rx_opcode_min_pcp[15:0] | I | rx_serdes_clk | Minimum priority control opcode value. |
| ctl_rx_opcode_max_pcp[15:0] | I | rx_serdes_clk | Maximum priority control opcode value. |
| ctl_rx_enable_gpp | I | rx_serdes_clk | A value of 1 enables global pause packet processing. |
| ctl_rx_check_mcast_gpp | I | rx_serdes_clk | A value of 1 enables global pause multicast destination address processing. |
| ctl_rx_check_ucast_gpp | I | rx_serdes_clk | A value of 1 enables global pause unicast destination address processing. |
| ctl_rx_check_sa_gpp | I | rx_serdes_clk | A value of 1 enables global pause source address processing. |
| ctl_rx_check_etype_gpp | I | rx_serdes_clk | A value of 1 enables global pause ethertype processing. |
| ctl_rx_etype_gpp[15:0] | I | rx_serdes_clk | Ethertype field for global pause processing. |
| ctl_rx_check_opcode_gpp | I | rx_serdes_clk | A value of 1 enables global pause opcode processing. |
| ctl_rx_opcode_gpp[15:0] | I | rx_serdes_clk | Global pause opcode value. |
| ctl_rx_enable_ppp | I | rx_serdes_clk | A value of 1 enables priority pause packet processing. |
| ctl_rx_check_mcast_ppp | I | rx_serdes_clk | A value of 1 enables priority pause multicast destination address processing. |
| ctl_rx_check_ucast_ppp | I | rx_serdes_clk | A value of 1 enables priority pause unicast destination address processing. |
| ctl_rx_check_sa_ppp | I | rx_serdes_clk | A value of 1 enables priority pause source address processing. |
| ctl_rx_check_etype_ppp | I | rx_serdes_clk | A value of 1 enables priority pause ethertype processing. |
| ctl_rx_etype_ppp[15:0] | I | rx_serdes_clk | Ethertype field for priority pause processing. |
| ctl_rx_check_opcode_ppp | I | rx_serdes_clk | A value of 1 enables priority pause opcode processing. |
| ctl_rx_opcode_ppp[15:0] | I | rx_serdes_clk | Priority pause opcode value. |
| stat_rx_pause_req[8:0] | O | rx_serdes_clk | Pause request signal. When the RX receives a valid pause frame, it sets the corresponding bit of this bus to a 1 and keeps it at 1 until the pause packet has been processed. See Pause Processing Interface for pause interface details. |
| ctl_rx_pause_ack[8:0] | I | rx_serdes_clk | Pause acknowledge signal. This bus is used to acknowledge the receipt of the pause frame from the user logic. See Pause Processing Interface for pause interface details. |
| ctl_rx_check_ack | I | rx_serdes_clk | Wait for acknowledge. If this input is set to 1, the 40G/50G High Speed Ethernet Subsystem uses the ctl_rx_pause_ack[8:0] bus for pause processing. If this input is set to 0, ctl_rx_pause_ack[8:0] is not used. |
| ctl_rx_forward_control | I | rx_serdes_clk | A value of 1 indicates that the 40G/50G High Speed Ethernet Subsystem forwards control packets to you. A value of 0 causes the 40G/ 50G High Speed Ethernet Subsystem to drop control packets. See Pause Processing Interface for control/pause packet processing. |
| stat_rx_pause_valid[8:0] | O | rx_serdes_clk | This bus indicates that a pause packet was received and the associated quanta on the stat_rx_pause_quanta[8:0][15:0] bus is valid and must be used for pause processing. If an 802.3x Ethernet MAC Pause packet is received, bit[8] is set to 1. |
| stat_rx_pause_quanta[8:0][15:0] | O | rx_serdes_clk | These nine buses indicate the quanta received for each of the eight priorities in priority-based pause operation and global pause operation. If an 802.3x Ethernet MAC Pause packet is received, the quanta are placed in value [8]. |