RX Path Control/Status Ports - 3.2 English

40G/50G High Speed Ethernet Subsystem Product Guide (PG211)

Document ID
PG211
Release Date
2021-10-27
Version
3.2 English

The following table describes the other status/control ports.

Table 1. RX Path Control/Status Signals
Name I/O Clock Domain Description
ctl_rate_mode I static This signal causes the IP core to switch between 50G operation (0) and 40G operation (1). Note that the clock frequencies will need to be correct for the mode chose.
ctl_rx_enable I rx_serdes_clk RX Enable. For normal operation, this input must be set to 1. When this input is set to 0, after the RX completes the reception of the current packet (if any), it stops receiving packets by keeping the PCS from decoding incoming data. In this mode, there are no statistics reported and the AXI4-Stream interface is idle.
ctl_rx_check_preamble I rx_serdes_clk When asserted, this input causes the Ethernet MAC to check the preamble of the received frame.
ctl_rx_check_sfd I rx_serdes_clk When asserted, this input causes the Ethernet MAC to check the start of frame Delimiter of the received frame.
ctl_rx_force_resync I rx_serdes_clk

RX force resynchronization input. This signal is used to force the RX path to reset, re-synchronize, and realign. A value of 1 forces the reset operation. A value of 0 allows normal operation.

Note: This input should normally be Low and should only be pulsed (1 cycle minimum pulse) to force realignment. CTL_RX_FORCE_RESYNC restarts the synchronization state machine but does not reset the GT logic. In most cases when there is an RX failure, the GT RX needs to be reset.
ctl_rx_delete_fcs I rx_serdes_clk Enable FCS removal by the RX core. If this bit is set to 0, the 40G/50G High Speed Ethernet Subsystem does not remove the FCS of the incoming packet. If this bit is set to 1, the 40G/50G High Speed Ethernet Subsystem deletes the FCS to the received packet. FCS is not deleted for packets that are 8 bytes long. This input should only be changed while the corresponding reset input is asserted.
ctl_rx_ignore_fcs I rx_serdes_clk

Enable FCS error checking at the

AXI4-Stream interface by the RX core. If this bit is set to 0, a packet received with an FCS error is sent with the rx_errout pin asserted during the last transfer (rx_eopout and rx_enaout sampled 1). If this bit is set to 1, the 40G/50G High Speed Ethernet Subsystem does not flag an FCS error at the AXI4-Stream interface.

Note: The statistics are reported as if the packet is good. The stat_rx_bad_fcs signal, however, reports the error.
ctl_rx_max_packet_len[14:0] I rx_serdes_clk

Any packet longer than this value is considered to be oversized. If a packet has a size greater than this value, the packet is truncated to this value and the rx_errout signal is asserted along with the rx_eopout signal. Packets less than 16 bytes are dropped. The allowed value for this bus can range from 64 to 16,383.

ctl_rx_max_packet_len[14] is reserved and must be set to 0.

ctl_rx_min_packet_len[7:0] I rx_serdes_clk

Any packet shorter than this value is considered to be undersized. If a packet has a size less than this value, the rx_errout signal is asserted during the rx_eopout asserted cycle. Packets that are less than 16 bytes are dropped.

Note: This value should be greater than or equal to 64B.
ctl_rx_vl_length_minus1[15:0] I rx_serdes_clk

Number of words in between PCS Lane markers minus one. Default value, as defined in IEEE Std 802.3-2015, should be set to 16,383. This input should only be changed while the corresponding reset input is asserted.

Note: When RS-FEC is enabled in the 50G core configuration, this value will be set to 20479.
ctl_rx_vl_marker_id[VL_LANES-1:0][63:0] I rx_serdes_clk These inputs set the PCS Lane markers for each PCS lane. These inputs should be set to the values as defined in the IEEE Std 802.3-2015. For IEEE 802.3 default values, see Section 5.3 [ IEEE Standard for Ethernet (IEEE Std 802.3-2015)]. This input should only be changed while the corresponding reset input is asserted.
stat_rx_framing_err_[VL_LANES-1:0][3:0] O rx_clk_out RX sync header bits framing error. Each PCS Lane has a four-bit bus that indicates how many sync header errors were received for that PCS Lane. The value of the bus is only valid when the corresponding stat_rx_framing_err_valid_[VL_LANES-1:0] is a 1. The values on these buses can be updated at any time and are intended to be used as increment values for sync header error counters.
stat_rx_framing_err_valid_[VL_LANES-1:0] O rx_clk_out Valid indicator for stat_rx_framing_err_[VL_LANES-1:0]. When one of these outputs is sampled as a 1, the value on the corresponding stat_rx_framing_err_[VL_LANES-1:0] is valid.
stat_rx_local_fault O rx_clk_out This output is High when stat_rx_internal_local_fault or stat_rx_received_local_fault is asserted. This output is level sensitive.
stat_rx_synced[VL_LANES-1:0] O rx_clk_out

Word Boundary Synchronized. These signals indicate whether a PCS lane is word boundary synchronized. A value of 1 indicates the corresponding PCS lane has achieved word boundary synchronization and it has received a PCS lane marker.

Corresponds to management data input/ output (MDIO) register bit 3.52.7:0 and 3.53.11:0 as defined in Clause 82.3. This output is level sensitive.

stat_rx_synced_err[VL_LANES-1:0] O rx_clk_out Word Boundary Synchronization Error. These signals indicate whether an error occurred during word boundary synchronization in the respective PCS lane. A value of 1 indicates that the corresponding PCS lane lost word boundary synchronization due to sync header framing bits errors or that a PCS lane marker was never received. This output is level sensitive.
stat_rx_mf_len_err[VL_LANES-1:0] O rx_clk_out

PCS Lane Marker Length Error. These signals indicate whether a PCS Lane Marker length mismatch occurred in the respective lane (that is, PCS Lane Markers were received not every ctl_rx_vl_length_minus1 words apart). A value of 1 indicates that the corresponding lane is receiving PCS Lane Markers at wrong intervals.

This remains High until the error condition is removed.

stat_rx_mf_repeat_err[VL_LANES-1:0] O rx_clk_out PCS Lane Marker Consecutive Error. These signals indicate whether four consecutive PCS Lane Marker errors occurred in the respective lane. A value of 1 indicates an error in the corresponding lane. This output remains High until the error condition is removed.
stat_rx_mf_err[VL_LANES-1:0] O rx_clk_out PCS Lane Marker Word Error. These signals indicate that an incorrectly formed PCS Lane Marker Word was detected in the respective lane. A value of 1 indicates an error occurred. This output is pulsed for one clock cycle to indicate the error condition. Pulses can occur in back-to-back cycles.
stat_rx_aligned O rx_clk_out All PCS Lanes Aligned/Deskewed. This signal indicates whether or not all PCS lanes are aligned and deskewed. A value of 1 indicates all PCS lanes are aligned and deskewed. When this signal is a 1, the RX path is aligned and can receive packet data. When this signal is 0, a local fault condition exists. This also corresponds to MDIO register bit 3.50.12 as defined in Clause 82.3. This output is level sensitive.
stat_rx_status O rx_clk_out

PCS status. A value of 1 indicates that the PCS is aligned and not in hi_ber state.

Corresponds to MDIO register bit 3.32.12 as defined in Clause 82.3. This output is level sensitive.

stat_rx_block_lock[VL_LANES-1:0] O rx_clk_out Block lock status for each PCS lane. A value of 1 indicates that the corresponding lane has achieved block lock as defined in Clause 82. Corresponds to MDIO register bit 3.50.7:0 and 3.51.11:0 as defined in Clause 82.3. This output is level sensitive.
stat_rx_aligned_err O rx_clk_out Loss of Lane Alignment/Deskew. This signal indicates that an error occurred during PCS lane alignment or PCS lane alignment was lost. A value of 1 indicates an error occurred. This output is level sensitive.
stat_rx_misaligned O rx_clk_out

Alignment Error. This signal indicates that the lane aligner did not receive the expected PCS lane marker across all lanes. This signal is not asserted until the PCS lane marker has been received at least once across all lanes and at least one incorrect lane marker has been received. This occurs one metaframe after the error.

This signal is not asserted if the lane markers have never been received correctly. Lane marker errors are indicated by the corresponding stat_rx_mf_err signal.

This output is pulsed for one clock cycle to indicate an error condition. Pulses can occur in back-to-back cycles.

stat_rx_remote_fault O rx_clk_out Remote fault indication status. If this bit is sampled as a 1, it indicates a remote fault condition was detected. If this bit is sampled as a 0, a remote fault condition does not exist. This output is level sensitive.
stat_rx_vl_number_[3:0]|1:0] O rx_clk_out

There are a total of VL_LANES separate stat_rx_vl_number[4|1:0] buses. stat_rx_vl_number_# indicates which PCS lane is being received on the corresponding physical lane. This bus is only valid when the corresponding bit of stat_rx_synced[VL_LANES-1:0] is a 1. These outputs are level sensitive.

stat_rx_vl_demuxed[VL_LANES-1:0] O rx_clk_out PCS Lane Marker found. If a signal of this bus is sampled as 1, it indicates that the receiver has properly de-muxed that PCS lane. These outputs are level sensitive.
stat_rx_bad_fcs[n:0] O rx_clk_out Bad FCS indicator. The value on this bus indicates packets received with a bad FCS, but not a stomped FCS. A stomped FCS is defined as the bitwise inverse of the expected good FCS. This output is pulsed for one clock cycle to indicate an error condition. Pulses can occur in back-to-back cycles.
stat_rx_stomped_fcs[n:0] O rx_clk_out Stomped FCS indicator. The value on this bus indicates packets were received with a stomped FCS. A stomped FCS is defined as the bitwise inverse of the expected good FCS. This output is pulsed for one clock cycle to indicate the stomped condition. Pulses can occur in back-to-back cycles.
stat_rx_truncated O rx_clk_out Packet truncation indicator. A value of 1 indicates that the current packet in flight is truncated due to its length exceeding ctl_rx_max_packet_len[14:0]. This output is pulsed for one clock cycle to indicate the truncated condition. Pulses can occur in back-to-back cycles.
stat_rx_internal_local_fault O rx_clk_out This signal goes High when an internal local fault is generated due to any one of the following: test pattern generation, bad lane alignment, or high bit error rate. This signal remains High as long as the fault condition persists.
stat_rx_received_local_fault O rx_clk_out This signal goes High when enough local fault words are received from the link partner to trigger a fault condition as specified by the IEEE fault state machine. This signal remains High as long as the fault condition persists.
stat_rx_bip_err[VL_LANES-1:0] O rx_clk_out BIP8 error indicator. A non-zero value indicates the BIP8 signature byte was in error for the corresponding PCS lane. A non-zero value is pulsed for one clock cycle. This output is pulsed for one clock cycle to indicate an error condition. Pulses can occur in back-to-back cycles.
stat_rx_hi_ber O rx_clk_out High Bit Error Rate (BER) indicator. When set to 1, the BER is too high as defined by IEEE Std 802.3-2015. Corresponds to MDIO register bit 3.32.1 as defined in Clause 82.3. This output is level sensitive.
ctl_rx_custom_preamble_enable I rx_clk_out When asserted, this signal causes the preamble to be presented on rx_preambleout.
rx_preambleout[55:0] O rx_clk This bus represents the preamble bytes when the ctl_rx_custom_preamble_enable signal is asserted. It is valid on the first cycle of the packet.