RX Path Control/Status/Statistics Signals - 3.2 English

40G/50G High Speed Ethernet Subsystem Product Guide (PG211)

Document ID
PG211
Release Date
2021-10-27
Version
3.2 English
Table 1. RX Path Control/Status/Statistics Signals
Name Size I/O Description
ctl_rx_test_pattern_* 1 I Test pattern checking enable for the RX core. A value of 1 enables test mode as defined in Clause 82.2.17. Corresponds to MDIO register bit 3.42.2 as defined in Clause 82.3. Checks for scrambled idle pattern.

This port is available when the AXI4-Lite interface is not selected.

ctl_rx_enable_* 1 I RX Enable. For normal operation, this input must be set to 1. When this input is set to 0, after the RX completes the reception of the current packet (if any), it stops receiving packets by keeping the PCS from decoding incoming data. In this mode, there are no statistics reported and the user interface is idle.

This port is available when the AXI4-Lite interface is not selected and core type is Ethernet MAC+PCS/PMA.

ctl_rx_delete_fcs_* 1 I Enable FCS removal by the RX core. If this bit is set to 0, the 40G/50G High Speed Ethernet Subsystem does not remove the FCS of the incoming packet. If this bit is set to 1, the 40G/50G High Speed Ethernet Subsystem deletes the FCS to the received packet. FCS is not deleted for packets that are =<8 bytes long. This input should only be changed while the corresponding reset input is asserted.

This port is available when the AXI4-Lite interface is not selected and core type is Ethernet MAC+PCS/PMA.

ctl_rx_ignore_fcs_* 1 I Enable FCS error checking at the user interface by the RX core. If this bit is set to 0, a packet received with an FCS error is sent with the rx_errout pin asserted during the last transfer (rx_eopout and rx_enaout sampled 1). If this bit is set to 1, the 40G/ 50G High Speed Ethernet Subsystem does not flag an FCS error at the user interface.

The statistics are reported as if the packet is good. The stat_rx_bad_fcs signal, however, reports the error.

This port is available when the AXI4-Lite interface is not selected and core type is Ethernet MAC+PCS/PMA.

ctl_rx_max_packet_len_* 15 I Any packet longer than this value is considered to be oversized. If a packet has a size greater than this value, the packet is truncated to this value and the rx_errout signal is asserted along with the rx_eopout signal. Packets less than 16 bytes are dropped. The allowed value for this bus can range from 64 to 16,383.

ctl_rx_max_packet_len[14] is reserved and must be set to 0.

This port is available when the AXI4-Lite interface is not selected and core type is Ethernet MAC+PCS/PMA.

ctl_rx_min_packet_len_* 8 I Any packet shorter than this value is considered to be undersized. If a packet has a size less than this value, the rx_errout signal is asserted during the rx_eopout asserted cycle. Packets that are less than 64 bytes are dropped.

This port is available when the AXI4-Lite interface is not selected and core type is Ethernet MAC+PCS/PMA.

ctl_rx_custom_preamble_enable_* 1 I When asserted, this signal causes the preamble to be presented on rx_preambleout.

This port is available when the AXI4-Lite interface is not selected and core type is Ethernet MAC+PCS/PMA and Include FIFO Logic is disabled)

ctl_rx_check_sfd_* 1 I When asserted, this input causes the Ethernet MAC to check the start of frame Delimiter of the received frame.

This port is available when the AXI4-Lite interface is not selected and core type is Ethernet MAC+PCS/PMA.

ctl_rx_check_preamble_* 1 I When asserted, this input causes the Ethernet MAC to check the preamble of the received frame.

This port is available when the AXI4-Lite interface is not selected and core type is Ethernet MAC+PCS/PMA.

ctl_rx_process_lfi_* 1 I When this input is set to 1, the RX core expects and processes LF control codes coming in from the SerDes. When set to 0, the RX core ignores LF control codes coming in from the SerDes.

This port is available when the AXI4-Lite interface is not selected and core type is Ethernet MAC+PCS/PMA.

ctl_rx_force_resync_* 1 I RX force resynchronization input. This signal is used to force the RX path to reset, re-synchronize, and realign. A value of 1 forces the reset operation. A value of 0 allows normal operation.
Note: This input should normally be Low and should only be pulsed (1 cycle minimum pulse) to force realignment.

This port is available when the AXI4-Lite interface is not selected and core type is Ethernet MAC+PCS/PMA.

stat_rx_block_lock_* 4 O Block lock status for each PCS lane. A value of 1 indicates that the corresponding lane has achieved block lock as defined in Clause 82. Corresponds to MDIO register bit 3.50.7:0 and 3.51.11:0 as defined in Clause 82.3. This output is level sensitive.
stat_rx_framing_err_valid_0 1 O Valid indicator for stat_rx_framing_err_0. When 1 stat_rx_framing_err_0 is valid.
stat_rx_framing_err_0 3 O RX sync header bits framing error. Each PCS Lane has a four-bit bus that indicates how many sync header errors were received for that PCS Lane. The value of the bus is only valid when the corresponding stat_rx_framing_err_valid_0 is a 1. The values on these buses can be updated at any time and are intended to be used as increment values for sync header error counters.
stat_rx_framing_err_valid_1 1 O Valid indicator for stat_rx_framing_err_1. When 1 stat_rx_framing_err_1 is valid.
stat_rx_framing_err_1 3 O RX sync header bits framing error. Each PCS Lane has a four-bit bus that indicates how many sync header errors were received for that PCS Lane. The value of the bus is only valid when the corresponding stat_rx_framing_err_valid_1 is a 1. The values on these buses can be updated at any time and are intended to be used as increment values for sync header error counters.
stat_rx_framing_err_valid_2 1 O Valid indicator for stat_rx_framing_err_2. When 1 stat_rx_framing_err_2 is valid.
stat_rx_framing_err_2 3 O RX sync header bits framing error. Each PCS Lane has a four-bit bus that indicates how many sync header errors were received for that PCS Lane. The value of the bus is only valid when the corresponding stat_rx_framing_err_valid_2 is a 1. The values on these buses can be updated at any time and are intended to be used as increment values for sync header error counters.
stat_rx_framing_err_valid_3 1 O Valid indicator for stat_rx_framing_err_3. When 1 stat_rx_framing_err_3 is valid.
stat_rx_framing_err_3 3 O RX sync header bits framing error. Each PCS Lane has a four-bit bus that indicates how many sync header errors were received for that PCS Lane. The value of the bus is only valid when the corresponding stat_rx_framing_err_valid_3 is a 1. The values on these buses can be updated at any time and are intended to be used as increment values for sync header error counters.
stat_rx_vl_demuxed_* 4 O PCS Lane Marker found. If a signal of this bus is sampled as 1, it indicates that the receiver has properly de-muxed that PCS lane.

This output is level sensitive.

stat_rx_vl_number_0 2 O The value of this bus indicates which physical lane appears on PCS lane 0. This bus is only valid when the corresponding bit of stat_rx_synced[PCS_LANES-1:0] is a

1. These outputs are level sensitive.

stat_rx_vl_number_1 2 O The value of this bus indicates which physical lane appears on PCS lane 1.
stat_rx_vl_number_2 2 O The value of this bus indicates which physical lane appears on PCS lane 2.
stat_rx_vl_number_3 2 O The value of this bus indicates which physical lane appears on PCS lane 3.
stat_rx_synced_* 4 O Word Boundary Synchronized. These signals indicate whether a PCS lane is word boundary synchronized. A value of 1 indicates the corresponding PCS lane has achieved word boundary synchronization and it has received a PCS lane marker.

Corresponds to MDIO register bit 3.52.7:0 and 3.53.11:0 as defined in Clause 82.3.

This output is level sensitive.

stat_rx_synced_err_* 4 O Word Boundary Synchronization Error. These signals indicate whether an error occurred during word boundary synchronization in the respective PCS lane. A value of 1 indicates that the corresponding PCS lane lost word boundary synchronization due to sync header framing bits errors or that a PCS lane marker was never received. This output is level sensitive.
stat_rx_mf_len_err_* 4 O PCS Lane Marker Length Error. These signals indicate whether a PCS Lane Marker length mismatch occurred in the respective lane (that is, PCS Lane Markers were received not every ctl_rx_vl_length_minus1 words apart). A value of 1 indicates that the corresponding lane is receiving PCS Lane Markers at wrong intervals. This remains High until the error condition is removed.
stat_rx_mf_repeat_err_* 4 O PCS Lane Marker Consecutive Error. These signals indicate whether four consecutive PCS Lane Marker errors occurred in the respective lane. A value of 1 indicates an error in the corresponding lane. This output remains High until the error condition is removed.
stat_rx_mf_err_* 4 O PCS Lane Marker Word Error. These signals indicate that an incorrectly formed PCS Lane Marker Word was detected in the respective lane. A value of 1 indicates an error occurred. This output is pulsed for one clock cycle to indicate the error condition. Pulses can occur in back-to-back cycles.
stat_rx_misaligned_* 1 O Alignment Error. This signal indicates that the lane aligner did not receive the expected PCS lane marker across all lanes. This signal is not asserted until the PCS lane marker has been received at least once across all lanes and at least one incorrect lane marker has been received. This occurs one metaframe after the error.

This signal is not asserted if the lane markers have never been received correctly. Lane marker errors are indicated by the corresponding stat_rx_mf_err signal.

This output is pulsed for one clock cycle to indicate an error condition. Pulses can occur in back-to-back cycles.

stat_rx_aligned_err_* 1 O Loss of Lane Alignment/Deskew. This signal indicates that an error occurred during PCS lane alignment or PCS lane alignment was lost. A value of 1 indicates an error occurred. This output is level sensitive.
stat_rx_bip_err_0_* 1 O BIP8 error indicator for PCS lane 0. A non-zero value indicates the BIP8

signature was in error. A non-zero value is pulsed for one clock cycle.

This output is pulsed for one clock cycle to indicate an error condition.

stat_rx_bip_err_1_* 1 O BIP8 error indicator for PCS lane 1.
stat_rx_bip_err_2_* 1 O BIP8 error indicator for PCS lane 2.
stat_rx_bip_err_3_* 1 O BIP8 error indicator for PCS lane 3.
stat_rx_aligned_* 1 O All PCS Lanes Aligned/Deskewed. This signal indicates whether or not all PCS lanes are aligned and deskewed. A value of 1 indicates all PCS lanes are aligned and deskewed. When this signal is a 1, the RX path is aligned and can receive packet data. When this signal is 0, a local fault condition exists. This also corresponds to MDIO register bit 3.50.12 as defined in Clause 82.3. This output is level sensitive.
stat_rx_hi_ber_* 1 O High Bit Error Rate (BER) indicator. When set to 1, the BER is too high as defined by IEEE Std 802.3-2015. Corresponds to MDIO register bit 3.32.1 as defined in Clause 82.3.

This output is level sensitive.

stat_rx_status_* 1 O PCS status. A value of 1 indicates that the PCS is aligned and not in hi_ber state.

Corresponds to Management Data Input/ Output (MDIO) register bit 3.32.12 as defined in Clause 82.3. This output is level sensitive.

stat_rx_bad_code_* 2 O Increment for 64B/66B code violations. This signal indicates that the RX PCS receive state machine is in the RX_E state as specified by the IEEE Std 802.3-2015. This output can be used to generate MDIO register 3.33:7:0 as defined in Clause 82.3.
stat_rx_bad_code_valid_* 1 O Indicates when stat_rx_bad_code is valid.

This port is available when core type is Ethernet PCS/PMA.

stat_rx_error_valid_* 1 O Indicates when stat_rx_error is valid.

This port is available when core type is Ethernet PCS/PMA.

stat_rx_error_* 8 O Test pattern mismatch increment. A non-zero value in any cycle indicates a

mismatch occurred for the test pattern in the RX core. This output is only active when ctl_rx_test_pattern is set to a 1. This output is pulsed for one clock cycle.

This port is available when core type is Ethernet PCS/PMA.

stat_rx_fifo_error_* 1 O Indicates when RX FIFO goes into an underflow or overflow condition.

If this output is sampled as a 1 in any clock cycle, the corresponding port must be reset to resume proper operation.

This port is available when core type is Ethernet PCS/PMA.

stat_rx_total_packets_* 2 O Increment for the total number of packets received.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_total_good_packets_* 1 O Increment for the total number of good packets received. This value is only

non-zero when a packet is received completely and contains no errors.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_total_bytes_* 6 O Increment for the total number of bytes received.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_total_good_bytes_* 14 O Increment for the total number of good bytes received. This value is only non-zero when a packet is received completely and contains no errors.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_packet_small_* 2 O Increment for all packets that are less than 64 bytes long. Packets that are less than 16 bytes are dropped.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_jabber_* 1 O Increment for packets longer than ctl_rx_max_packet_len with bad FCS.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_packet_large_* 1 O Increment for all packets that are more than 9,215 bytes long.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_oversize_* 1 O Increment for packets longer than ctl_rx_max_packet_len with good FCS.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_undersize_* 2 O Increment for packets shorter than stat_rx_min_packet_len with good FCS.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_toolong_* 1 O Increment for packets longer than ctl_rx_max_packet_len with good and bad FCS.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_fragment_* 2 O Increment for packets shorter than stat_rx_min_packet_len with bad FCS.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_packet_64_bytes_* 1 O Increment for good and bad packets received that contain 64 bytes.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_packet_65_127_bytes_* 1 O Increment for good and bad packets received that contain 65 to 127 bytes.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_packet_128_255_bytes_* 1 O Increment for good and bad packets received that contain 128 to 255 bytes.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_packet_256_511_bytes_* 1 O Increment for good and bad packets received that contain 256 to 511 bytes.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_packet_512_1023_bytes_* 1 O Increment for good and bad packets received that contain 512 to 1,023 bytes.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_packet_1024_1518_bytes_* 1 O Increment for good and bad packets received that contain 1,024 to 1,518 bytes.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_packet_1519_1522_bytes_* 1 O Increment for good and bad packets received that contain 1,519 to 1,522 bytes.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_packet_1523_1548_bytes_* 1 O Increment for good and bad packets received that contain 1,523 to 1,548 bytes.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_packet_1549_2047_bytes_* 1 O Increment for good and bad packets received that contain 1,549 to 2,047 bytes.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_packet_2048_4095_bytes_* 1 O Increment for good and bad packets received that contain 2,048 to 4,095 bytes.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_packet_4096_8191_bytes_* 1 O Increment for good and bad packets received that contain 4,096 to 8,191 bytes.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_packet_8192_9215_bytes_* 1 O Increment for good and bad packets received that contain 8,192 to 9,215 bytes.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_bad_fcs_* 2 O Bad FCS indicator. The value on this bus indicates packets received with a bad FCS, but not a stomped FCS. A stomped FCS is defined as the bitwise inverse of the expected good FCS. This output is pulsed for one clock cycle to indicate an error condition. Pulses can occur in back-to-back cycles.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_packet_bad_fcs_* 1 O Increment for packets between 64 and ctl_rx_max_packet_len bytes that have FCS errors.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_stomped_fcs_* 2 O Stomped FCS indicator. The value on this bus indicates packets were received with a stomped FCS. A stomped FCS is defined as the bitwise inverse of the expected good FCS. This output is pulsed for one clock cycle to indicate the stomped condition. Pulses can occur in back-to-back cycles.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_bad_preamble_* 1 O Increment bad preamble. This signal indicates if the Ethernet packet received was preceded by a valid preamble. A value of 1 indicates that an invalid preamble was received.
Note: When an invalid preamble is detected, the stat_rx_bad_preamble signal is asserted regardless of the setting of the ctl_rx_check_preamble signal.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_bad_preamble_* 1 O Increment bad SFD. This signal indicates if the Ethernet packet received was preceded by a valid SFD. A value of 1 indicates that an invalid SFD was received.
Note: When an invalid SFD is detected, the stat_rx_bad_preamble signal is asserted regardless of the setting of the ctl_rx_check_preamble signal.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_got_signal_os_* 1 O Signal OS indication. If this bit is sampled as a 1, it indicates that a Signal OS word was received.
Note: Signal OS should not be received in an Ethernet network.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_test_pattern_mismatch_* 2 O Test pattern mismatch increment. A nonzero value in any cycle indicates how many mismatches occurred for the test pattern in the RX core. This output is only active when ctl_rx_test_pattern is set to a 1. This output can be used to generate MDIO register 3.43.15:0 as defined in Clause 82.3. This output is pulsed for one clock cycle.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_truncated_* 1 O Packet truncation indicator. A value of 1 indicates that the current packet in flight is truncated due to its length exceeding ctl_rx_max_packet_len[14:0]. This output is pulsed for one clock cycle to indicate the truncated condition. Pulses can occur in back-to-back cycles.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_local_fault_* 1 O This output is High when stat_rx_internal_local_fault or stat_rx_received_local_fault is asserted. This output is level sensitive.
stat_rx_remote_fault_* 1 O Remote fault indication status. If this bit is sampled as a 1, it indicates a remote fault condition was detected. If this bit is sampled as a 0, a remote fault condition does not exist. This output is level sensitive.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_internal_local_fault_* 1 O This signal goes High when an internal local fault is generated due to any one of the following: test pattern generation, bad lane alignment, or high bit error rate. This signal remains High as long as the fault condition persists.

This port is available when core type is Ethernet MAC+PCS/PMA.

stat_rx_received_local_fault_* 1 O This signal goes High when enough local fault words are received from the link partner to trigger a fault condition as specified by the IEEE fault state machine. This signal remains High as long as the fault condition persists.

This port is available when core type is Ethernet MAC+PCS/PMA.