Receive - 3.2 English

40G/50G High Speed Ethernet Subsystem Product Guide (PG211)

Document ID
PG211
Release Date
2021-10-27
Version
3.2 English

The receive block implements the frame alignment state diagram illustrated in IEEE 802.3 Clause 72, Figure 72-4.

Frame Lock State Machine
The frame lock state machine searches for the frame marker, consisting of 16 consecutive 1s followed by 16 consecutive 0s. This functionality is fully specified in IEEE 802.3 Clause 72, Figure 72-4. When frame lock has been achieved, the signal frame_lock is set to a value of TRUE.
Received Data
The receiver outputs the control channel with the bit definitions previously defined in the previous two tables and signal names defined in Port Descriptions. If a DME_error has occurred during the reception of a particular DME frame, the control channel outputs are not updated but retain the value of the last received good DME frame and are updated when the next good DME frame is received.