Receive AXI4-Stream Interface – 256-bit - 3.2 English

40G/50G High Speed Ethernet Subsystem Product Guide (PG211)

Document ID
PG211
Release Date
2021-10-27
Version
3.2 English
Table 1. Receive AXI4-Stream Interface
Name I/O Clock Domain Description
rx_axis_tdata[255:0] O tx_clk_out AXI4-Stream Data to user logic
rx_axis_tvalid O tx_clk_out AXI4-Stream Data Valid. When this signal is 1, there is valid data on the RX AXI bus.
rx_axis_tuser O tx_clk_out AXI4-Stream User Sideband interface.
  • 1 indicates a bad packet has been received.
  • 0 indicates a good packet has been received.
rx_axis_tlast O rx_clk_out AXI4-Stream signal indicating an end of packet
rx_axis_tkeep[31:0] O rx_clk_out AXI4-Stream Data Control to upper layer.