The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 10/27/2021 Version 3.2 | |
| N/A | Updated for Versal GTM support |
| Common Transceiver Ports for Versal ACAP | Updated the table in the section. |
| MODE_REG: 0008 | Updated the table. |
| STAT_GT_WIZ_REG: 04A0 | Updated the table. |
| SerDes Data Mapping for GTM | Updated the table. |
| 08/09/2021 Version 3.2 | |
| Entire document | Editorial updates. |
| 08/06/2021 Version 3.2 | |
| RX and TX PCS Lane Marker Values | Updated the table in the section. |
| GT Selection and Configuration Tab | Updated images and table. |
| RX Path Control/Status/Statistics Signals | Updated the table in the section. |
| TX Pause Interface Control/Status/Statistics Signals | Updated the table in the section. |
| RX Pause Interface Control/Status/Statistics Signals | Updated the table in the section. |
| IEEE 1588 TX/RX Interface Control/Status/Statistics Signals | Updated the table in the section. |
| Clause 91 RS-FEC Interface Control/Status/Statistics Signals | Updated topic |
| 02/04/2021 Version 3.2 | |
| General updates | Added support for Versal ACAP |
| 06/03/2020 Version 3.1 | |
| Board Testing of the 40G/50G High Speed Ethernet Using the AXI4-Lite Interface | Topic updated |
| LogiCORE Example Design Clocking and Resets | Diagrams updated |
| Customizing and Generating the Subsystem | Vivado graphics updated |
| Example Design Hierarchy (GT in Example Design) | Graphic updated |
|
Debugging Auto-Negotiation and Link Training Debugging Auto-Negotiation and Link Training Using AXI4-Lite Interface |
Debugging topics added |
| 10/30/2019 Version 3.0 | |
| Board Testing of the 40G/50G High Speed Ethernet Using the AXI4-Lite Interface | Added new section |
| 05/22/2019 Version 2.5 | |
| Entire document | Updated the GTM clocking and reset diagrams. |
| Designing with the Subsystem | Added a new table |
| 12/05/2018 Version 2.4 | |
| Entire document | Added the GTM clocking and reset diagrams. RSFEC clause updated from 108 to 91. |
| 04/04/2018 Version 2.3 | |
| Latency | Updated tables Added a note for the |
| Design Flow Steps | Updated figures Added a table note for the GT RefClk (In MHz) option Fixed typo: “udp” replaced with “upd” |
| AXI4-Lite Interface Implementation | Added .h Header File description |
| 12/20/2017 Version 2.3 | |
| Please Read: Important Legal Notices | Updated |
| Product Specification |
Updated 3.42.3 to 3.42.7 in the Description
for Updated description for |
| Example Design | Added a note about an invalid preamble in the tables Updated description for |
| 10/04/2017 Version 2.3 | |
| Overview | Updated tables |
| Product Specification | Added RX and TX Latency values Updated figures Added clarification text to the first paragraph of the Back to Back Continuous Transfer section Added note about STAT_*_MSB/LSB registers to Statistics Counters section Added text below SWITCH_CORE_SPEED_REG: 018C table about Runtime Switch mode. |
| Egress | Added latency values |
| Design Flow Steps | Updated screen displays Removed AN/LT Clock option from tables. |
| Changes from v2.2 to v2.3 | Added new section |
| 06/07/2017 Version 2.2 | |
| Licensing and Ordering | Updated the Ordering information |
| Latency | Updated tables. Replaced 64 bytes with 16 bytes for several signals. |
| Designing with the Subsystem | Updated screen displays |
| Changes from v2.1 to v2.2 | Added new section |
| 04/05/2017 Version 2.1 | |
| Features | Added two new features |
| IP Facts | Updated Supported User Interfaces row with 128-bit straddle interfaces |
| Overview | Updated |
| Standards | Updated |
| Product Specification | Added new figures |
| Design Flow Steps | Updated figures |
| TX Pause Generation | Added an important note |
| References | Updated |
| 11/30/2016 Version 2.0 | |
| Product Specification |
Changed “tx_reset and rx_reset” to “s_axi_aresetn” and changed “active-High” to “active-Low” in the second sentence of the Configuration Registers subsection of the AXI4-Lite Register Space |
| Design Flow Steps | Updated the tables to add table notes |
| Example Design | Added text about clearing status registers to the Status
Registers section Added text about clearing statistics counters to the Statistics Counters section |
| 10/05/2016 Version 2.0 | |
| Entire document | Added tick_reg_mode_sel
references |
| Designing with the Subsystem | Updated figures |
| Design Flow Steps | Updated figures |
| RS-FEC Support | Added new section |
| Example Design Hierarchy (GT in Example Design) | Added new section |
| Latency | Added new section |
| Run Time Switchable | Added new section |
| Product Specification | Added new Register information |
| 06/08/2016 Version 1.1 | |
| Product Specification | Updated figures |
| Designing with the Subsystem | Updated figures |
| Design Flow Steps | Updated figures |
| Upgrading | Added ports and modified port names. |
| Entire document | Changed “HSEC” to “40G/50G High Speed Ethernet Subsystem” Changed 50GMII to XL/50GMII throughout |
| TX Debug (Buffer Errors) | Updated description |
| 04/06/2016 Version 1.0 | |
| Initial release | N/A |