- RX
- Each SerDes lane has its own recovered clock. This clock is used for all of the logic for that SerDes lane. The 40G/50G High Speed Ethernet Subsystem synchronizes the received data from all of the SerDes to the RX core clock domains. There is one clock per SerDes lane. The SerDes clock frequency is equal to the data rate divided by the SerDes width. For example, at a data rate of 25.78125 Gb/s per lane and a 66-bit SerDes, the clock frequency is 25.78125e9/66=390.625 MHz.
- TX
- The TX SerDes domain is associated with the TX lane logic. Both TX transceivers must be clocked with the same frequency. The frequency is calculated in the same way as documented in RX.