For comprehensive information about Vivado® simulation components, as well as information about using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation (UG900).
A demonstration simulation test bench is part of each release. Simulation is performed on the included encrypted RTL. The test bench consists of a loopback from the TX side of the user interface, through the TX circuit, looping back to the RX circuit, and checking the received packets at the RX side of the user interface.
The loopback simulation includes a path through the transceiver. The simulation is run using the provided Linux scripts for several common industry-standard simulators.
For more information, see Test Bench.
Simulation can take a long time to complete due to the time required to complete alignment. A `define SIM_SPEED_UP is available to improve simulation time by reducing the PCS lane Alignment Marker (AM) spacing in order to speed up the time the IP will take to achieve alignment. Setting `define SIM_SPEED_UP will reduce CTL_TX_VL_LENGTH_MINUS1 and CTL_RX_VL_LENGTH_MINUS1.
The SIM_SPEED_UP option can be used for simulation when in serial loopback or if the Alignment Marker spacing can be reduced at both endpoints. This option is compatible with the example design simulation which uses serial loopback.
- SIM_SPEED_UP is only available when running RTL simulation. It is not available when running simulation with post synthesis or post implementation netlist.
- Altering the value of CTL_TX_VL_LENGTH_MINUS1 and CTL_RX_VL_LENGTH_MINUS1 from the default value will violate the IEEE 802.3 specification.
- Decreasing the AM spacing will result in less bandwidth being available on the link. When using the PCS only core, the TX core does not provide back pressure to the user logic and the reduced bandwidth can cause stat_tx_fifo_error when transmitting larger back-to-back packets.
- This change can be made only in simulation. For a design to work in hardware, the default IEEE value must be used.
- Full rate simulation without the SIM_SPEED_UP option should still be run.
VCS
Use the vlogan option: +define+SIM_SPEED_UP.
ModelSim
Use the vlog option: +define+SIM_SPEED_UP.
Questa Advanced Simulator
Use the vlog option: +define+SIM_SPEED_UP
Xcelium Parallel Simulator
Use the xmvlog option: +define+SIM_SPEED_UP
Vivado Simulator
Use the xvlog option: -d SIM_SPEED_UP.
RS-FEC Enabled Configuration Simulation
For faster simulation, apply SIM_SPEED_UP and deselect the Use Precompiled IP simulation libraries checkbox in the Settings window, as shown in the following figures. If this is not done, the simulation can run for a long time, timing out with an error.
